Yongping Chen

Design and performance of a low noise circuit for VLWIR HgCdTe photoconductive detectors

Due to VLWIR (very long wavelength infrared) signals are often very weak, it is about 1uV, little disturb can affect the performance of the total detector system very much. In order to achieve high Signal-to-Noise ratio, it is expected that the circuit can be designed to work as close as to the HgCdTe IR detector. That is to say the circuit can work normally at low temperature 77K even more low. On the other hand, according to the characteristics of a Very Long Wavelength HgCdTe photoconductive detector, its resistance is about 25Ω~50Ω, CMOS circuit for this low resistance is very difficult. In this paper, A new kind of circuit for this low resistance detector is designed. The operation principle and noise of the circuit are analyzed. The noise model of the circuit is given. An expression for its equivalent input noise is derived. This circuit for long wave photoconductive detector was implemented in 0.5μm CMOS process. The size of twenty-cell chip is 3mm×4mm and its noise performance is tested. The test result indicate that this circuit can work normally at low temperature 77K, the equivalent input noise is less than 1uV. This circuit is suit to many kinds of low resistance detector. The voltage gain is more than 10000. The linearity has been reached 90%. Finally, it can work normally either by ±2 or by ±1.5 voltage power supply. The bandwidth is more than 5Khz.

Design and implementation of a high-performance readout circuit for uncooled infrared detector

At present, most uncooled infrared detectors circuits consist of the corresponding blind pixel detector, which increases the complexity of uncooled infrared detector, and the performance of the readout circuits is not ideal in practical applications. In order to achieve high performance of the readout circuit for uncooled infrared detectors, a kind of readout circuit based on current mirror has been designed in this paper. The readout circuit is composed of current mirror input part, capacitor feedback transimpedance amplifier (CTIA) and correlated double sampling (CDS) output circuit. Transconductance amplifier CTIA with capacitance negative feedback is used in the circuit and it consists of three integral capacitors, thus the circuit can realize different magnifications. The CDS N SF (source follow) and P SF are adopted as the circuit’s output, the output swing can easily be greater than 2V. In average, the CDS N SF and P SF’s power consumption is very low. So the total power consumption of 160 line circuit is about 100 mW. The non-uniformity of circuit has been obviously improved by reasonable parameter settings. In the test, the non-uniformity of the readout circuit has reached 1%. The other test results of total power consumption and the output amplitude also agree with simulation results. When the readout circuit and uncooled infrared detector are connected, the infrared signal can be well read out. the device has good noise characteristics and the NETD(noise equivalent temperature difference) is near 80mK. When the integration time is 20μs, the whole device’s response is about 15mV/K.

A low-temperature bridge-input CMOS circuit for low-impedance detector

Low-impedance long-wave infrared detectors (the wavelength longer than 10 microns) have very important applications in cryogenic aim detection, super-distance detection, anti-jamming target identify and so on. Therefore the research in the field of infrared detector technology is of importance. At present, no low-impedance photoconductive detectors are integrated with CMOS circuit. To design low-temperature CMOS circuit being fit for low impedance infrared photoconductive detector and realize high performance IR imaging, using differential amplifier with symmetrical positive and negative power is necessary, the low-resist detector is connected between an input and grounding, the corresponding low resistance is connected between another input and grounding, a larger feedback resistor is used between negative input and output, this structure can effectively solve the matching problem of low-impedance and high-impedance CMOS. In addition, the noise voltage from VBIAS terminal can be effectively reduced by increasing the ratio of the bias resistor and the detector resistance. The whole circuit is designed two grade. The first grade is adopted bridge input structure, this structure is fit for low impedance detector. The positive amplifying method is applied in second grade . The first grade feedback resistance is designed 1M ohm, the circuit is supplied by ±1.5V. The testing showed that the circuit can work well when it connects with low-impedance infrared photoconductive detector at the liquid nitrogen low temperature. The magnification is up to 30000 times, 3dB bandwidth is more than 4kHz, the equivalent input noise is near 1.5 micron volts. This circuit has perfectly solved the matching problem between high impedance CMOS circuit and low impedance detector.

A high speed and high gain CMOS receiver chip for a pulsed time-of-flight laser rangefinder

An integrated receiver channel for a pulsed time-of-flight (TOF) laser rangefinder has been designed. Pulsed TOF laser range finding devices using a laser diode transmitter can achieve millimeter-level distance measurement accuracy in a measurement range of several tens of meters to non-cooperative targets. The amplifier exploits the regulated cascade (RGC) configuration as the input-stage, thus achieving as large effective input trans-conductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. To enlarge the bandwidth, inductive peaking technology has been adopted. An active inductor (MOS-L) is used instead of spiral inductor in CMOS process. An R-2R resistor ladder is inserting between per-amplifier and post-amplifier as the variable attenuator for digital gain control purpose. The gain-bandwidth of a basic differential pair with resistive load is not large enough for broad band operation. A circuit solution to improve both gain and bandwidth of an amplifying stage is proposed. Traditional and modified Cherry-Hooper amplifiers are discussed and the cascading of several stages to constitute the post-amplifier is designed. The fully integrated one-chip solution is designed with Cadence IC design platform. The simulation result shows the bandwidth of the trans-impedance amplifier is 215MHz with the presence of a 2pF input capacitor and 5pF load capacitor. And the maximum trans-impedance gain is 136dB. The walk error is less than 1ns in 1:1000 dynamic range. The responsive time is less than 2.2ns.

A cryogenic temperature eight-cell CMOS differential current amplifier for IR detectors

In order to make medium-long wave HgCdTe IR detector work normally it must be in zero bias voltage, the differential input current preamplifier can easily make HgCdTe IR detector biased at zero voltage. Because IR signals are often very weak, then little disturb can affect the performance of the total detector system very much. In order to achieve high Signal-to-Noise ratio, it is expected that the differential input current preamplifier can be designed to work as close as to the HgCdTe IR detector. That is to say the preamplifier can also work normally at 77K. In this paper, a high-performance low-noise differential input current preamplifier working at cryogenic temperature for HgCdTe IR detectors is designed. Since a differential input folded-cascode structure has been used in the preamplifiers design, it makes that the gain of single stage amplifier can arrive 60dB, the circuit uses high resistant poly as feedback resistance so that 40 MΩ feedback resistance can be integrated on chip at temperature 77k ,which can directly transforms IR detectors current to voltage, avoiding the additional noise by using exterior resister. The preamplifiers noise characteristics were analyzed and the methods for decreasing noise were proposed. This differential input current preamplifier was implemented in 0.5μm CMOS process. The size of eight-cell chip is 3mm×1.9mm. The test result shows that the current preamplifier has good performance at the temperature of 77K. Within the bandwidth of 3.3KHz, the total output voltage noise is 120uV, the equivalent total input noise voltage is 3PA, the equivalent input noise current is 0.03pA/Hz1/2@100Hz. The preamplifier power consumption is less than 1mW at 77K. When the input current is less than 10nA, its linearity has been reached 99%. This circuit can work normally at temperature between 300K to 77K and it can be used for several bands of IR detector. Finally, it can work normally either by ±2 or by ±1.5 voltage power supply. This current preamplifier has been successfully applied in the signal readout of HgCdTe IR detectors for infrared imaging.

The optimization of noise and dynamic range with variable-gain column amplifier in CMOS image sensors

A low noise and relatively high dynamic range CMOS active pixel sensor (APS) using a variable-gain column amplifier is presented and analyzed. On this signal path there are a pixel source follower, a switched-capacitor, noise-cancelling, variable-gain amplifier, and a correlated double sample (CDS) circuit in each column. The using of high gain for the column amplifier reduces input-referred random noise, but it may reduce the dynamic range of this device at meanwhile. In this paper, we present a detail analysis for the noise and the dynamic range with the variable gain of the column amplifier. It is revealed that the total random read noise can be analyzed in three parts: the first part is from the pixel circuit, including the pixel-related fixed-pattern noise, reset noise and pixel source follower amplifier noise; the second part is from the column circuit, including the column-related fixed-pattern noise and the column amplifier noise; and the third part is from the output amplifier in the chip-level circuit. The analysis suggests that the noise components from the pixel and column can be significantly cancelled by the double-stage column noise canceller, and the noise components from the output amplifier in the chip-level circuit, are the major noise source and can be greatly reduced if the signal is amplified before this noise is added. Both the analysis and measured result indicate that we can achieve a low input-referred noise and keep a relatively high dynamic gain by choosing a proper column amplifier gain.

Design and Performance of a Preamplifier for HgCdTe IR Detectors

In this paper, A high-performance low-power low-noise preamplifier working at lower temperature (about 90K) for HgCdTe IR detectors is designed by using a single-ended folded-cascode structure and by using an MOS transistor operating in the linear region as feedback resistor. Its noise characteristics were analyzed and the methods for decreasing noise were put forward. This preamplifier was fabricated in 1.2 y- m CMOS technology. The size of four cell chip is 2.1mm times 2.9mm. The test result shows that the preamplifier can work at the temperature of 90K. The equivalent input noise current is 0.03pA/Hzfrac12@100Hz and the power consumption is less than 1mW . This preamplifier works well when it be used in conjunction with HgCdTe IR detectors, and the performance has good linearity