Yongquan Qu

High speed graphene transistors with a self-aligned nanowire gate

Graphene has attracted considerable interest as a potential new electronic material. With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics. However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance. Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co2Si–Al2O3 core–shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA μm−1) and transconductance (1.27 mS μm−1) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of fT = 100–300 GHz, with the extrinsic fT (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic fT of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths.

Plasmonic Modulation of the Upconversion Fluorescence in NaYF4:Yb/Tm Hexaplate Nanocrystals using Gold Nanoparticles or Nanoshells

Automatic upgrade: attachment of gold nanoparticles (NPs) onto upconversion nanocrystals (NCs) results in plasmonic interactions that lead to a significant enhancement of upconversion emission of more than 2.5. Conversely, formation of a gold shell greatly suppresses the NC emission because of considerable scattering of excitation irradiation (see picture; a=NC before seed attachment; b, c=NC with attached Au NPs; c=NC with Au shell; scale bar=50 nm).

Electrically conductive and optically active porous silicon nanowires.

We report the synthesis of vertical silicon nanowire array through a two-step metal-assisted chemical etching of highly doped n-type silicon (100) wafers in a solution of hydrofluoric acid and hydrogen peroxide. The morphology of the as-grown silicon nanowires is tunable from solid nonporous nanowires, nonporous/nanoporous core/shell nanowires, to entirely nanoporous nanowires by controlling the hydrogen peroxide concentration in the etching solution. The porous silicon nanowires retain the single crystalline structure and crystallographic orientation of the starting silicon wafer and are electrically conductive and optically active with visible photoluminescence. The combination of electronic and optical properties in the porous silicon nanowires may provide a platform for novel optoelectronic devices for energy harvesting, conversion, and biosensing.

Graphene‐Supported Hemin as a Highly Active Biomimetic Oxidation Catalyst

Well supported: stable hemin-graphene conjugates formed by immobilization of monomeric hemin on graphene, showed excellent catalytic activity, more than 10 times better than that of the recently developed hemin-hydrogel system and 100 times better than that of unsupported hemin. The catalysts also showed excellent binding affinities and catalytic efficiencies approaching that of natural enzymes.

Towards highly efficient photocatalysts using semiconductor nanoarchitectures

The search for clean renewable energy sources is of central importance to address the ever-increasing challenges of diminishing fossil fuels and global warming. Photocatalytic processes can mimic natural photosynthesis to directly convert solar energy into chemical energy, and represent an attractive strategy for renewable energy generation and environmental remediation. Nanostructured semiconductors can play an important role in photocatalysis due to their unique structures, and chemical and physical properties. Here we present a brief overview of the recent progress in the development of semiconductor nanostructure based photocatalysts. In particular, we focus our discussions on four essential problems that dictate the performance of a photocatalyst material: visible light absorption for efficient solar energy harvesting, efficient charge separation and transportation, effective cocatalysts for efficient charge utilization, and photoelectrochemical stability for robust photocatalysis. Challenges, potential solutions, and recent efforts to address each one of these problems are discussed. Lastly, we finish the perspective with the discussion of a recent concept of using freestanding photoelectrochemical nanodevices as a potential solution to a new generation of highly efficient and stable photocatalysts.

Unveiling the Formation Pathway of Single Crystalline Porous Silicon Nanowires

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H(2)O(2)) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H(2)O(2)) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and renucleate on the sidewalls of nanowires to initiate new etching pathways to produce a porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 to 30 m(2) g(-1) and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy.

Sub-100 nm channel length graphene transistors

Here we report high-performance sub-100 nm channel length graphene transistors fabricated using a self-aligned approach. The graphene transistors are fabricated using a highly doped GaN nanowire as the local gate with the source and drain electrodes defined through a self-aligned process and the channel length defined by the nanowire size. This fabrication approach allows the preservation of the high carrier mobility in graphene and ensures nearly perfect alignment between source, drain, and gate electrodes. It therefore affords transistor performance not previously possible. Graphene transistors with 45-100 nm channel lengths have been fabricated with the scaled transconductance exceeding 2 mS/μm, comparable to the best performed high electron mobility transistors with similar channel lengths. Analysis of and the device characteristics gives a transit time of 120-220 fs and the projected intrinsic cutoff frequency (f(T)) reaching 700-1400 GHz. This study demonstrates the exciting potential of graphene based electronics in terahertz electronics.

High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

Deposition of high-κ dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-κ dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-κ dielectrics with graphene by first synthesizing freestanding high-κ oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al2O3 nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm2/V·s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-κ dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics.

pH-Operated Mechanized Porous Silicon Nanoparticles

Porous silicon nanoparticles (PSiNPs) were synthesized by silver-assisted electroless chemical etching of silicon nanowires generated on a silicon wafer. The rod-shaped particles (200-400 nm long and 100-200 nm in diameter) were derivatized with a cyclodextrin-based nanovalve that was closed at the physiological pH of 7.4 but open at pH <6. Release profiles in water and tissue culture media showed that no cargo leaked when the valves were closed and that release occurred immediately after acidification. In vitro studies using human pancreatic carcinoma PANC-1 cells proved that these PSiNPs were endocytosed and carried cargo molecules into the cells and released them in response to lysosomal acidity. These studies show that PSiNPs can serve as an autonomously functioning delivery platform in biological systems and open new possibilities for drug delivery.

High-Performance Top-Gated Graphene-Nanoribbon Transistors Using Zirconium Oxide Nanowires as High-Dielectric-Constant Gate Dielectrics

Graphene has attracted a great deal of interest in the past several years.[1–5] New physics has been predicted and observed, such as ultrahigh carrier mobility,[6] electron-hole symmetry and quantum hall effect,[2, 4, 7–9] and the strong suppression of weak localization.[10–12] For mainstream logic application, graphene nanoribbons (GNRs), as thin strips of graphene or unrolled carbon nanotubes, are predicted to be semiconducting due to edge effects and quantum confinement.[13–15] Recent experimental studies have also demonstrated that GNRs can effectively function as a semiconducting channel for room-temperature field-effect transistors.[16–22] By varying the width of GNRs at selected points, it is also possible to create graphene quantum dots within a GNR for single electron transistors.[23] These studies represent important advances in GNR based electronics. However, most of the efforts to date employ a silicon substrate as a global back gate and silicon oxide as the gate dielectrics. While such a device has led to many interesting scientific discoveries, it will be of limited use for practical applications due to the high gate switching voltage required and the inability to independently address multiple units on the same chip.[17, 20, 21] Top-gated devices with high-k dielectrics can significantly reduce the required switching voltage and allow independently addressable device arrays and functional circuits, and therefore are of significant interest.