Yongru Gu

High-Speed Architecture Design of Tomlinson–Harashima Precoders

Like decision feedback equalizers (DFEs), Tomlinson-Harashima precoders (TH precoders) contain nonlinear feedback loops, which limit their use for high-speed applications. Unlike in DFEs where the output levels of the nonlinear devices are finite, in TH precoders, theoretically, the output levels of the modulo devices are infinite. Thus, it is difficult to apply look-ahead and pre-computation techniques to pipeline TH precoders, which were successfully applied to pipeline infinite-impulse response (IIR) filters and DFEs in the past. In this paper, three approaches are proposed to design high-speed TH precoders. In the first approach, the traditional block processing technique for DFEs is generalized to the design of high-speed TH precoders. In the second approach, based on the equivalent form of a TH precoder where the precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a finite-level compensation signal, two high-speed pipelined designs are developed. In the third approach, parallel processing techniques for fast IIR filters are generalized to the design of parallel TH precoders.

Pipelining Tomlinson-Harashima precoders

Like decision feedback equalizers (DFEs), Tomlinson-Harashima precoders (TH precoders) contain nonlinear feedback loops, which limit their use for high speed applications. Unlike in DFEs where the output levels of the nonlinear devices are finite, in TH precoders the output levels of the modulo devices are infinite, or finite but very large. Thus, it is difficult to apply look-ahead and pre-computation techniques to pipeline TH precoders, which were successfully applied to pipeline IIR filters and DFEs in the past. However, a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a finite-level compensation signal. Based on this point of view, this paper presents a novel approach to pipeline the TH precoder.

Novel FEXT Cancellation and Equalization for High Speed Ethernet Transmission

In high-speed multi-pair wireline communication systems, such as 10 gigabit Ethernet over Copper (10GBASE-T), far-end crosstalk (FEXT) becomes a major impairment and needs to be suppressed to increase data rates. Conventional techniques based on crosstalk cancellation are not suitable for FEXT due to the fact that the disturbing source of FEXT is generally unknown to the victims. This paper presents two different approaches to efficiently deal with FEXT over unshielded twisted-pair (UTP) copper cables. To eliminate the error propagation problem in practice, both approaches use the Tomlinson-Harashima precoding (THP) technique which however makes the transceiver design nontrivial. In the first approach, FEXT is treated as noise and a new feedforward FEXT canceller is proposed. Compared with conventional techniques, the proposed FEXT canceller can mitigate the non-causal part of FEXT, thus leading to better FEXT cancellation performance. In the second approach, FEXT is treated as signal, and the general multi-input multi-output (MIMO) equalization technique is combined with the TH precoding technique to deal with both intersymbol interference (ISI) and FEXT. Different from the existing works, the proposed designs comply with the 10GBASE-T standard and they are suitable in real applications. Simulation results verify that the proposed approaches can achieve much better performance in terms of decision-point signal-to-noise ratio (DP-SNR) than conventional techniques. It is also shown that the hardware complexity of the transceiver can be reduced by about 37.2% by utilizing the increased DP-SNR in the proposed designs.

Low-Complexity Echo and NEXT Cancellers for High-Speed Ethernet Transceivers

Gigabit and multigigabit transceivers require very long adaptive filters for echo and near-end crosstalk (NEXT) cancellation. Implementation of these filters not only occupies large silicon area but also consumes significant power. These problems become even worse when the Tomlinson-Harashima precoding (THP) technique is used in applications such as 10-Gigabit Ethernet over Copper (10 GBASE-T) as the input to the echo and NEXT cancellers is no longer a simple PAM-M signal. To reduce the complexity of these cancellers, in this paper, a novel method based on word-length reduction technique is proposed. The proposed design is derived by replacing the original input to the echo and NEXT cancellers with a finite-level signal, which is the sum of the input to the TH precoder and a finite-level compensation signal. Then, this modified input signal is recoded to have shorter word-length compared with the original input. Hence, the overall complexity can be reduced by using the proposed method. To further reduce the complexity of these cancellers, an improved design is proposed by exploiting the property of the compensation signal. Compared with the traditional design, the proposed echo and NEXT cancellers have exact input and do not suffer from the quantization problem, and thus they are more suitable for VLSI implementation. The proposed method can also be applied to design adaptive echo and NEXT cancellers with little modification. The performance evaluation is performed by simulations to verify the proposed design. It is shown that, by applying the proposed method to a 10 GBASE-T Ethernet system, the hardware complexity of echo and NEXT cancellers can be reduced by about 10.82% without performance loss, compared with the traditional design.

MIMO Equalization and Cancellation for 10Gbase-T 1

Traditionally equalization is performed individually for 10GBASE-T, and FEXT is treated as noise to be cancelled at the receiver. However, FEXT contains information about the symbols transmitted from remote transmitters and it can be viewed as a signal rather than noise to facilitate signal recovery. This paper proposes to use MIMO (multi-input multi output) equalization technique to deal with FEXT in 10GBASE-T. In the proposed MIMO technique, FEXT is treated as signal, which improves SNR. Instead of using long FEXT cancellers, MIMO-DFE with short length is used to remove post-cursor ISI. Our simulation results show that, by using the proposed MIMO equalization, we are able to achieve SNR (signal to noise ratio) improvement around 0.5-9 dB with 13% less complexity than the traditional equalization technique in twisted-pair channel environment

Design of Parallel Tomlinson–Harashima Precoders

Like decision feedback equalizers (DFEs), Tomlinson-Harashima precoders (TH precoders) contain nonlinear feedback loops, which limit their use for high-speed applications. Unlike in DFEs, where the output levels of the nonlinear devices are finite, in TH precoders the output levels of the modulo devices are either infinite or finite but very large. Thus, it is difficult to apply look-ahead and pre-computation techniques to speed up TH precoders, which were successfully applied to design parallel and pipelined infinite impulse response (IIR) filters and DFEs in the past. However, a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a finite-level compensation signal. Based on this point of view, a novel parallel architecture is proposed to speed up TH precoders. This architecture can be used in many high-speed applications, such as 10-Gb Ethernet over copper.

Interleaved trellis coded modulation and decoding for 10 Gigabit Ethernet over copper

It is highly likely that 10 Gigabit Ethernet over copper (10GBASE-T) transceivers will use a 10-level pulse amplitude modulation (PAM 10) as well as a 4D trellis code as in 1000BASE-T. The traditional trellis coded modulation scheme, as in 1000BASE-T, leads to a design where the corresponding decoder with a long critical path needs to operate at 833 MHz. It is difficult to meet the critical path requirements of such a decoder. To solve the problem, two interleaved trellis coded modulation schemes are proposed. The inherent decoding speed requirements are relaxed by factors of 4 and 2, respectively. Parallel decoding of the interleaved codes requires multiple decoders. To reduce the hardware overhead, time-multiplexed or folded decoder structures are proposed where only one decoder is needed and each delay in the decoder is replaced with four delays for scheme 1 and two delays for scheme 2, respectively. These delays can be used to reduce the critical path. Compared with the conventional decoder, the folded decoders for the two proposed schemes can achieve speedups of 4 and 2, respectively. Simulation results show that the error-rate performances of the two schemes are quite close to that of the conventional scheme.

Complexity reduction of the decoders for interleaved trellis coded modulation schemes for 10 gigabit Ethernet over copper

10GBASE-T (10 gigabit Ethernet over unshielded twisted pairs) will probably use a 10-level pulse amplitude modulation (PAM10) as well as a 4D trellis code similar to the one in 1000BASE-T (1000 megabit Ethernet over copper medium). The trellis code can be used in a conventional way as in 1000BASE-T, but the corresponding decoder with a long critical path needs to operate at 833 MHz. To solve the problem, two interleaved trellis coded modulation schemes were proposed in our previous work. The inherent decoding speed requirements can be relaxed by factors of 4 and 2, respectively. Due to intersymbol interference (ISI), the branch metric units in the decoders corresponding to the two interleaved modulation schemes are much more complicated than those in the conventional decoder. Thus, this paper considers the problem of complexity reduction of the decoders for the two interleaved modulation schemes. Two complexity reduction schemes are proposed. Simulation results show that the performance loss due to complexity reduction is negligible.

Pipelined Parallel Decision-Feedback Decoders for High-Speed Ethernet Over Copper

One of the powerful yet simple algorithms to decode trellis codes as well as to combat intersymbol interference (ISI) is the parallel decision-feedback decoding algorithm. However, for high-speed applications, such as Gigabit Ethernet over copper (1000BASE-T), the design and implementation of a parallel decision-feedback decoder (PDFD) is challenging due to the long critical path in the decoder structure. Straightforward pipelined designs usually introduce significant hardware overhead. To solve these problems, in this paper, first, based on an optimized scheduling of the computations in the parallel decision-feedback decoding algorithm, a low-complexity pipelined PDFD is proposed. Next, a novel retiming and reformulation technique is presented for the decision-feedback unit (DFU) in the PDFD, which can remove the DFU from the critical path of the PDFD with negligible hardware overhead. Based on these two techniques, two modified low-complexity pipelined PDFDs are derived. Compared with similar designs in the literature, the proposed design can reduce hardware overhead by 60% while achieving similar speed-up for Gigabit Ethernet systems. The savings are even greater for a pulse amplitude modulation (PAM) system with larger constellation

Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper

There were several modulation and coding proposals for 10GBASE-T (10 Gigabit Ethernet over copper) systems. One of these is based on a 10-level pulse amplitude modulation (PAM-10) combined with a 4D (four-dimensional) 8-state trellis code similar to the one in 1000BASE-T (1000 Megabit Ethernet over copper). The trellis code can be used in a conventional manner as in 1000BASE-T, but the corresponding decoder with a long critical path needs to operate at 833 MHz. It is difficult to meet the critical path requirements of such a decoder. To solve the problem, two interleaved trellis coded modulation schemes are proposed in this paper. The inherent decoding speed requirements can be relaxed by factors of 4 and 2, respectively. Due to intersymbol interference (ISI), the branch metric units in the decoders corresponding to the two interleaved modulation schemes are much more complicated than those in the conventional decoder. Thus this paper also considers the problem of complexity reduction of the decoders for the two proposed interleaved modulation schemes, and presents two novel complexity reduction schemes. Simulation results show that the error-rate performances of the two proposed interleaved schemes are quite close to that of the conventional scheme. It is also shown that the performance loss due to complexity reduction is negligible.