Yoo-Chan Jeon

Pd induced lateral crystallization of amorphous Si thin films

A thin palladium layer (∼40 A) was selectively formed on top of amorphous silicon films before annealing and the effects of palladium layer on the crystallization behavior of the amorphous silicon films were investigated. It was observed that the amorphous silicon right under the Pd layer could be crystallized to grain sizes of several hundred angstroms by annealing at 500 °C. In addition, the area between the Pd thin pads, patterned by lithography, was found to be crystallized to grain sizes of a few tens of microns in length by the same annealing. Such lateral crystallization was found to reach more than 100 μm in some cases. The lateral crystallization phenomenon might be useful for the fabrication of low temperature polycrystalline‐Si thin film transistors, providing large‐grained Si films.

Improvement of leakage currents of Pt/(Ba, Sr)TiO3/Pt capacitors

Pt/(Ba, Sr)TiO3/Pt capacitors fabricated by sputtering technique showed abnormally higher leakage current when negative bias was applied to the top electrode. In this letter, two kinds of processes were attempted to reduce high leakage current of Pt/BST/Pt capacitors for dynamic random access memory devices: (1) postannealing under O2 atmosphere and (2) adding oxygen into sputtering gas of platinum top electrode. These processes were very effective to reduce the oxygen vacancy in the BST films which are mostly responsible for such a high leakage current. The higher reverse currents were significantly lowered by these processes, so that we could obtain symmetric current versus voltage curves of Pt/BST/Pt capacitors.

Investigation of Ruthenium Electrodes for (Ba,Sr)TiO3 Thin Films

Ru/(Ba, Sr)TiO3(BST)/Ru capacitors were fabricated on TiN/Ti/Poly-Si/SiO2/Si substrate by sputtering technique. The effects of the bottom ruthenium electrode, deposited at various temperatures, on the characteristics of Ru/BST/Ru capacitor were intensively studied. Sputtered ruthenium films were grown in a columnar structure with a grain size ~30 nm. With an increasing deposition temperature of ruthenium films, the (002) preferred orientation and grain size of ruthenium films gradually increased while the residual compressive stress in the ruthenium films was reduced. The surface of ruthenium films was oxidized to form RuOx on its surface during the deposition of BST films, which dramatically changed the surface morphology of ruthenium films and affected the characteristics of Ru/BST/Ru capacitor. In this work, the electrical properties of Ru/BST/Ru capacitors are explained with an emphasis on the surface morphology and residual stress of ruthenium films.

I‐V characteristics of electron‐cyclotron‐resonance plasma‐enhanced chemical‐vapor‐deposition silicon nitride thin films

Silicon nitride thin films were fabricated by electron‐cyclotron‐resonance plasma‐enhanced chemical‐vapor deposition (ECR PECVD) at room temperature and current‐voltage characteristics were analyzed. A ledge in the first I‐V curve always appeared in ECR PECVD silicon nitride films and then disappeared in the subsequent I‐V curves. It turned out that the trapped charges caused by injection of electrons were responsible for the ledge in the I‐V curves of fresh samples. A new conduction mechanism for low electric field was proposed, namely trapping current by tunneling. This model turned out to be very successful to explain the low‐field I‐V characteristics in ECR‐PECVD silicon nitride films, such as temperature dependence of I‐V curves and the reverse current phenomenon. Computer simulation suggested the trapping cross section as 1×10−16 cm2 and the trap density as 7×1018 cm−3. The calculated trapping cross section corresponds to that of the neutral trap centers, which agrees well with the experimental results.

Electrical Stress Effect on Poly-Si Thin Film Transistors Fabricated by Metal Induced Lateral Crystallization

Electrical stress effects on polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated by metal induced lateral crystallization at 500° C have been investigated. Leakage current decreased by four orders of magnitude after the electrical stress in both n-channel TFTs and p-channel TFTs. It turned out that the electrical stress between the drain and source was more effective than that between the gate and source. Polarity of the electrical stress turned out to be also important for depression of the leakage current.

Thermal stability of metal electrodes (Pt, Ru, & Ir) on polycrystalline silicon in ferroelectric capacitors

Abstract Electrode materials such as Pt, Ru, and Ir on polycrystalline silicon were annealed and the thermal stability was investigated to check the feasibility of the structure. Sputtered Pt reacted with silicon to form PtSi at a low temperature of 400 °C and the top layer of silicide was oxidized in oxygen ambient. Ru and Ir films by sputtering were also silicidized above 550 °C and it made voids beneath silicide layers. All of the films are found to allow oxygen to diffuse through them and to get the underlying layers oxidized. However, Ir deposited by e-beam evaporation did not form silicide up to 700 °C and did not get oxidized up to 550 °C. Ir also allowed oxygen diffusion when annealed at 550 °C or lower temperature, but it was prevented when annealed at 700 °C.

Room Temperature Fabrication of Micro-Crystalline Silicon Films for Tft's By Ecr Pecvd

Microcrystalline silicon films were formed at room temperature without hydrogen dilution by ECR PECVD. Microwave power more than 400 W was necessary to get crystalline films and the crystallinity increased with the power thereafter. Addition of hydrogen and argon enhanced the crystalline phase formation and the deposition rate, the reason of which was found that hydrogen etched silicon films and argon addition drastically increased the etch rate. Annealing of the films showed that microcrystalline silicon films formed by ECR PECVD have a small fraction of amorphous phase. TFTs using silicon nitride and doped/undoped microcrystalline silicon films were fabricatedd with whole processes at room temperature.

Electrical Properties of Silicon Nitride Thin Films Fabricated by ECR PECVD at Room Temperature

Silicon nitride thin films were deposited on single crystalline silicon substrates at room temperature by ECR PECVD with SiH 4 and N 2 as source gases and the electrical properties were analyzed. The dominant conduction mechanism in a high field was Poole-Frenkel emission. A ledge in I-V curve was observed in the first voltage ramp and it was found to originate from the field reduction at the injecting electrode due to the charge trapped in deep traps in the film. It also turned out that the ledge is a characteristic of monopolar conduction. A new interpretation of the current at low field — tunneling into trap states — was proposed and the current variations according to the field and temperature could be well explained.