Yookun Cho

A space-efficient flash translation layer for CompactFlash systems

Flash memory is becoming increasingly important as nonvolatile storage for mobile consumer electronics due to its low power consumption and shock resistance. However, it imposes technical challenges in that a write should be preceded by an erase operation, and that this erase operation can be performed only in a unit much larger than the write unit. To address these technical hurdles, an intermediate software layer called a flash translation layer (FTL) is generally employed to redirect logical addresses from the host system to physical addresses in flash memory. Previous approaches have performed this address translation at the granularity of either a write unit (page) or an erase unit (block). We propose a novel FTL design that combines the two different granularities in address translation. This is motivated by the idea that coarse grain address translation lowers the resources required to maintain translation information, which is crucial in mobile consumer products for cost and power consumption reasons, while fine grain address translation is efficient in handling small size writes. Performance evaluation based on trace-driven simulation shows that the proposed scheme significantly outperforms previously proposed approaches.

LRFU: a spectrum of policies that subsumes the least recently used and least frequently used policies

Efficient and effective buffering of disk blocks in main memory is critical for better file system performance due to a wide speed gap between main memory and hard disks. In such a buffering system, one of the most important design decisions is the block replacement policy that determines which disk block to replace when the buffer is full. In this paper, we show that there exists a spectrum of block replacement policies that subsumes the two seemingly unrelated and independent Least Recently Used (LRU) and Least Frequently Used (LFU) policies. The spectrum is called the LRFU (Least Recently/Frequently Used) policy and is formed by how much more weight we give to the recent history than to the older history. We also show that there is a spectrum of implementations of the LRFU that again subsumes the LRU and LFU implementations. This spectrum is again dictated by how much weight is given to recent and older histories and the time complexity of the implementations lies between O(1) (the time complexity of LRU) and {\rm O}(\log_2 n) (the time complexity of LFU), where n is the number of blocks in the buffer. Experimental results from trace-driven simulations show that the performance of the LRFU is at least competitive with that of previously known policies for the workloads we considered.

On the existence of a spectrum of policies that subsumes the least recently used (LRU) and least frequently used (LFU) policies

Sam H. Nohs Sang Lyul Mint t Department of Computer Engineering Seoul National University Seoul 151-742, Korea http://ssrnet.snu.ac.kr http://archi.snu.ac.kr We show that there exists a spectrum of block replacement policies that subsumes both the Least Recently Used (LRU) and the Least Frequently Used (LFU) policies. The spectrum is formed according to how much more weight we give to the recent history than to the older history, and is referred to as the LRFU (Least Recently/Frequently Used) policy. Unlike many previous policies that use limited history to make block replacement decisions, the LRFU policy uses the complete reference history of blocks recorded during their cache residency. Nevertheless, the LRFU requires only a few words for each block to maintain such history. This paper also describes an implementation of the LRFU that again subsumes the LRU and LFU implementations. The LRFU policy is applied to buffer caching, and results from trace-driven simulations show that the LRFU performs better than previously known policies for the workloads we considered. This point is reinforced by results from our integration of the LRFU into the FreeBSD operating system.

Multifactor-dimensionality reduction shows a two-locus interaction associated with Type 2 diabetes mellitus.

Aims/hypothesisType 2 diabetes mellitus is a complex genetic disease, which results from interactions between multiple genes and environmental factors without any single factor having strong independent effects. This study was done to identify gene to gene interactions which could be associated with the risk of Type 2 diabetes.MethodsWe genotyped 23 different loci in the 15 candidate genes of Type 2 diabetes in 504 unrelated Type 2 diabetic patients and 133 non-diabetic control subjects. We analysed gene to gene interactions among 23 polymorphic loci using the multifactor-dimensionality reduction (MDR) method, which has been shown to be effective for detecting and characterising gene to gene interactions in case-control studies with relatively small samples.ResultsThe MDR analysis showed a significant gene to gene interaction between the Ala55Val polymorphism in the uncoupling protein 2 gene (UCP2) and the 161C>T polymorphism in the exon 6 of peroxisome proliferator-activated receptor γ (PPARγ) gene. This interaction showed the maximum consistency and minimum prediction error among all gene to gene interaction models evaluated. Moreover, the combination of the UCP2 55 Ala/Val heterozygote and the PPARγ 161 C/C homozygote was associated with a reduced risk of Type 2 diabetes (odds ratio: 0.51, 95% CI: 0.34 to 0.77, p=0.0016).Conclusions/interpretationUsing the MDR method, we showed a two-locus interaction between the UCP2 and PPARγ genes among 23 loci in the candidate genes of Type 2 diabetes. The determination of such genotype combinations contributing to Type 2 diabetes mellitus could provide a new tool for identifying high-risk individuals.

EARQ: Energy Aware Routing for Real-Time and Reliable Communication in Wireless Industrial Sensor Networks

Wireless industrial sensor networks are wireless sensor networks which have been adapted to industrial applications. Most techniques for wireless sensor networks can be applied to wireless industrial sensor networks. However, for industrial applications of wireless industrial sensor networks, new requirements such as real-time, reliable delivery need to be considered. In this paper, we propose EARQ, which is a novel routing protocol for wireless industrial sensor networks. It provides real-time, reliable delivery of a packet, while considering energy awareness. In EARQ, a node estimates the energy cost, delay and reliability of a path to the sink node, based only on information from neighboring nodes. Then, it calculates the probability of selecting a path, using the estimates. When packet forwarding is required, it randomly selects the next node. A path with lower energy cost is likely to be selected, because the probability is inversely proportional to the energy cost to the sink node. To achieve real-time delivery, only paths that may deliver a packet in time are selected. To achieve reliability, it may send a redundant packet via an alternate path, but only if it is a source of a packet. Experimental results show that EARQ is suitable for industrial applications, due to its capability for energy efficient, real-time, reliable communications.

PEACH: Power-efficient and adaptive clustering hierarchy protocol for wireless sensor networks

The main goal of this research is concerning clustering protocols to minimize the energy consumption of each node, and maximize the network lifetime of wireless sensor networks. However, most existing clustering protocols consume large amounts of energy, incurred by cluster formation overhead and fixed-level clustering, particularly when sensor nodes are densely deployed in wireless sensor networks. In this paper, we propose PEACH protocol, which is a power-efficient and adaptive clustering hierarchy protocol for wireless sensor networks. By using overhearing characteristics of wireless communication, PEACH forms clusters without additional overhead and supports adaptive multi-level clustering. In addition, PEACH can be used for both location-unaware and location-aware wireless sensor networks. The simulation results demonstrate that PEACH significantly minimizes energy consumption of each node and extends the network lifetime, compared with existing clustering protocols. The performance of PEACH is less affected by the distribution of sensor nodes than other clustering protocols.

Common genetic polymorphisms in the promoter of resistin gene are major determinants of plasma resistin concentrations in humans

Aims/hypothesisResistin is thought to be an important link between obesity and insulin resistance. It has been suggested that genetic polymorphism in the promoter of resistin gene is a determinant of resistin mRNA expression and possibly associated with obesity and insulin resistance. In this study, we investigated the association between the genotype of resistin promoter and its plasma concentrations.MethodsWe examined g.-537A>C and g.-420C>G polymorphisms in the resistin promoter and measured plasma resistin concentrations in Korean subjects with or without Type 2 diabetes. We also did haplotype-based promoter activity assays and the gel electrophoretic mobility shift assay.ResultsThe −420G and the −537A alleles, which were in linkage disequilibrium, were associated with higher plasma resistin concentrations. Individuals with haplotype A-G (−537A and −420G) had significantly higher plasma resistin concentrations than the others. Haplotype A-G had modestly increased promoter activity compared to the other haplotypes. Electrophoretic mobility shift assay showed that the −420G allele is specific for binding of nuclear proteins from adipocytes and monocytes. However, none of the two polymorphisms were associated with Type 2 diabetes or obesity in our study subjects.Conclusions/interpretationPolymorphisms in the promoter of resistin gene are major determinants of plasma resistin concentrations in humans.

Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture

Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.

Towards application/file-level characterization of block references: a case for fine-grained buffer management

Two contributions are made in this paper. First, we show that system level characterization of file block references is inadequate for maximizing buffer cache performance. We show that a finer-grained characterization approach is needed. Though application level characterization methods have been proposed, this is the first attempt, to the best of our knowledge, to consider file level characterizations. We propose an Application/File-level Characterization (AFC) scheme where we detect on-line the reference characteristics at the application level and then at the file level, if necessary. The results of this characterization are used to employ appropriate replacement policies in the buffer cache to maximize performance. The second contribution is in proposing an efficient and fair buffer allocation scheme. Application or file level resource management is infeasible unless there exists an allocation scheme that is efficient and fair. We propose the ΔHIT allocation scheme that takes away a block from the application/file where the removal results in the smallest reduction in the number of expected buffer cache hits. Both the AFC and ΔHIT schemes are on-line schemes that detect and allocate as applications execute. Experiments using trace-driven simulations show that substantial performance improvements can be made. For single application executions the hit ratio increased an average of 13 percentage points compared to the LRU policy, with a maximum increase of 59 percentage points, while for multiple application executions, the increase is an average of 12 percentage points, with a maximum of 32 percentage points for the workloads considered.

Genetic association study of adiponectin polymorphisms with risk of Type 2 diabetes mellitus in Korean population

Aims  To investigate any association between Type 2 diabetes mellitus and two single nucleotide polymorphisms (SNPs) in the adiponectin gene, T45G and G276T, in the Korean population.