Yoontaek Lee

The incidence, risk factors and prognostic implications of venous thromboembolism in patients with gastric cancer

Summary.  Background: Data on venous thromboembolism (VTE) in gastric cancer (GC) are very scarce. Objective: To investigate the incidence, risk factors and prognostic implications of VTE in Asian GC patients. Methods: Prospective databases containing clinical information on GC patients (n = 2,085) were used. Results: The 2‐year cumulative incidences of all VTE events were 0.5%, 3.5% and 24.4% in stages I, II–IV(M0) and IV(M1), respectively. Advanced stage, older age and no major surgery were independent risk factors for developing VTE. When the VTE cases were classified into extremity venous thrombosis (EVT), pulmonary thromboembolism (PTE) or intra‐abdominal venous thrombosis (IVT), IVTs (62%) were more common than EVTs (21%) or PTEs (17%). Although peri‐operative pharmacologic thromboprophylaxis was not routinely administered, the VTE incidence after major surgery was only 0.2%. During chemotherapy, EVT/PTE developed more frequently than IVT (54% vs. 19%); however, during untreated or treatment‐refractory periods, IVT developed more frequently than EVT/PTE (69% vs. 36%). In multivariate models, the development of EVT/PTE was a significant predictor of early death when compared with no occurrence of VTE (P < 0.05). However, IVT did not affect survival. Conclusion: This is the largest study that specially focused on VTE in GC and the VTE incidence in Asian GC patients was first demonstrated. Considering the low incidence of post‐operative VTE development, the necessity of peri‐operative pharmacologic thromboprophylaxis should be evaluated separately in Asian patients. The clinical situation of the development of EVT/PTE and IVT differed. Only EVT/PTE had an adverse effect on survival and IVT had no prognostic significance.

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

A 9.2 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast settling without exhibiting overshoots. While most previously reported peaking-free PLLs require additional circuit components which may adversely affect clock jitter or increase hardware complexity, the presented PLL requires only a new type of digital loop filter. The analysis on the loop dynamics and design of the optimal loop filter are presented. As for the implementation, a low-power linear time-to-digital converter (TDC) is realized with a set of three binary phase-frequency detectors whose triggering clocks are dithered using a delta-sigma modulator and phase interpolators. A digitally controlled oscillator (DCO) is implemented as a transformer-tuned LC oscillator whose frequency is set by a ratio between two digitally controlled currents. The digital PLL prototype, fabricated in a 65 nm CMOS, demonstrates 1.2 ps rms integrated jitter at 9.2 GHz and 1.58 μs settling time with 700 kHz bandwidth while dissipating 63.9 mW at a 1.2 V nominal supply.

A 15-V, 40-kHz class-D gate driver IC with 62% energy recycling rate

This paper presents a new type of gate driver IC that can significantly reduce the gate switching loss by leveraging high-speed and low-power operation of custom integrated circuits. The gate driver itself works as a mini bidirectional buck converter, which charges and discharges the gate terminal of a power device (e.g. IGBT) by feeding a chain of short pulses whose widths gradually increase or decrease into an LC filter. A set of circuit techniques to minimize the energy consumption in generating these pulses at the required frequency of up to 50-MHz and duty-cycle resolution of 5% is presented. A prototype IC fabricated in a 0.25-μm HV CMOS demonstrates 27.8-mW power consumption or equivalently 62% energy recycling while switching a 120-nC IGBT at 40-kHz and 15-V.

A 9–11-Bit Phase-Interpolating Digital Pulsewidth Modulator With 1000x Frequency Range

A design of a new hybrid-type digital pulsewidth modulator (DPWM) with a wide frequency range of 1000:1, from 10 kHz to 10 MHz, is presented. The proposed DPWM has the maximum duty-cycle resolution of 11 bits and consumes the power of 17.5 μW at 10 kHz and 2.36 mW at 10 MHz, respectively. The proposed DPWM realizes the upper 5-bit resolution using a programmable digital counter and the lower 6-bit resolution using a current-integrating-type phase interpolator, employing an M2M-ladder current-steering digital-to-analog converter for low power consumption. The operating clock is generated in on-chip using a relaxation oscillator. The prototype integrated circuit fabricated in a 0.25-μm high-voltage complementary metal-oxide-semiconductor demonstrates that the proposed DPWM maintains a good linearity across the entire operating range.

A 9.2-GHz digital phase-locked loop with peaking-free transfer function

This paper describes a digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer. That is the PLLs second-order transfer function does not have a closed-loop zero. Such a PLL does not exhibit overshoots in the phase step response and achieves fast settling. Unlike the previously-reported peaking-free PLLs the proposed PLL implements the peaking-free loop filter directly in digital domain without requiring additional components. A time-to-digital converter (TDC) is implemented as a set of three binary phase-frequency detectors that oversample the timing error with time-varying offsets achieving a linear TDC gain and PLL bandwidth insensitive to the jitter condition. And a 9.2-GHz digitally-controlled LC oscillator (DCO) with transformer-based tuning realizes a predictable DCO gain set by a ratio between two digitally-controlled currents. The prototype 9.2-GHz-output digital PLL fabricated in a 65nm CMOS demonstrates a fast settling time of 1.58-μs with 690-kHz bandwidth. The PLL has a 3.477-psrms divided clock jitter and -120dBc/Hz phase noise at 10MHz offset while dissipating 63.9-mW at a 1.2-V supply.

Electronic skins for soft, compact, reversible assembly of wirelessly activated fully soft robots

A skin-like driving system enables compact and reversible assembly of wirelessly activated, fully soft robots. Designing softness into robots holds great potential for augmenting robotic compliance in dynamic, unstructured environments. However, despite the body’s softness, existing models mostly carry inherent hardness in their driving parts, such as pressure-regulating components and rigid circuit boards. This compliance gap can frequently interfere with the robot motion and makes soft robotic design dependent on rigid assembly of each robot component. We present a skin-like electronic system that enables a class of wirelessly activated fully soft robots whose driving part can be softly, compactly, and reversibly assembled. The proposed system consists of two-part electronic skins (e-skins) that are designed to perform wireless communication of the robot control signal, namely, “wireless inter-skin communication,” for untethered, reversible assembly of driving capability. The physical design of each e-skin features minimized inherent hardness in terms of thickness (<1 millimeter), weight (~0.8 gram), and fragmented circuit configuration. The developed e-skin pair can be softly integrated into separate soft body frames (robot and human), wirelessly interact with each other, and then activate and control the robot. The e-skin–integrated robotic design is highly compact and shows that the embedded e-skin can equally share the fine soft motions of the robot frame. Our results also highlight the effectiveness of the wireless inter-skin communication in providing universality for robotic actuation based on reversible assembly.

Solo Single-Incision Laparoscopic Resectional Roux-en-Y Gastric Bypass for Morbid Obesity with Metabolic Syndrome

With the advancement of laparoscopic devices and surgical technology, the era of minimal invasive surgery has progressed to reduced-port surgery, and finally to single-incision laparoscopic surgery (SILS). Several reports show successful application of SILS to various types of bariatric surgery. Oftentimes, this requires a skilled and experienced scopist to perform the procedure. To overcome the technical difficulties of single-incision Roux-en-Y gastric bypass, a manual scope holder was used instead of an assistant scopist, greatly stabilizing the field of view. This allows the surgery to be performed at any time without being influenced by the need of a highly experienced scopist. In this report, we describe in detail the world’s first solo single-incision laparoscopic resectional Roux-en-Y gastric bypass.

Laparoscopic proximal gastrectomy for upper third early gastric cancer

Laparoscopic proximal gastrectomy is theoretically superior to total gastrectomy in the treatment of upper third early gastric cancer, as the former is less invasive and better preserves function. Three major issues have limited the more widespread use of proximal gastrectomy: its oncologic safety, functional benefits, and risk of reflux esophagitis. Many recent studies suggest that the oncologic safety of laparoscopic proximal and total gastrectomy is similar, with proximal gastrectomy resulting in improved functional outcomes. To date, however, no standard reconstruction method has been developed to effectively prevent reflux esophagitis after proximal gastrectomy. Our recent retrospective study found that no patient who underwent laparoscopic proximal gastrectomy with double tract reconstruction experienced severe reflux esophagitis and that this method was superior to laparoscopic total gastrectomy in preventing anemia and vitamin B12 deficiency. This result led to the design of a randomized controlled trial, the Korean Laparoendoscopic Gastrointestinal Surgery Study (KLASS) 05 (ClinicalTrials.gov; identifier: NCT02892643), which is currently comparing laparoscopic proximal gastrectomy with double tract reconstruction with laparoscopic total gastrectomy. This trial may help surgeons choose the optimal surgical approach and strategy for patients with proximal early gastric cancer.

GaN FET-based synchronous buck converter with 10-bit 4-MHz digital pulse width modulator

Architecture of the gallium nitride (GaN) FET-based synchronous buck converter with 10-bit, 4-MHz digital pulse width modulator (DPWM) is presented. The DPWM integrated in proposed architecture has a high resolution and a high operating frequency. In addition, the proposed architecture can control its duty-cycle and dead-time of PWM outputs detail by this DPWM. The testing board, which is manufactured by discrete devices and a custom IC, demonstrates 26.9-W with 91.3% efficiency of the power stage at 4-MHz switching frequency. Experimental results also show the wide duty-range operation controlled by the DPWM.

A 9–11 bits phase-interpolating digital pulse-width modulator with 1000X frequency range

A design of a new hybrid-type digital pulse-width modulator (DPWM) with a 1000:1 frequency range from 10kHz to 10-MHz, maximum resolution of 11-bits, and power dissipation of 2.36-mW is presented. The key to such a wide frequency range and low power dissipation is to use a phase interpolator circuit for fine duty-cycle adjustment instead of the delay lines used in the previous literature. The proposed hybrid DPWM realizes the upper 5-bit resolution using a digital counter and lower 6-bit using a phase interpolator. The prototype IC fabricated in a 0.25-μm HV CMOS demonstrates the 1000:1 frequency range and excellent linearity for 9~11-bit resolutions.