Yoshiaki Inada

A 1/1.8-inch 6.4MPixel 60 frames/s CMOS Image Sensor with Seamless Mode Change

A1/1.8-inch 6.4Mpixel 60frames/s CMOS image sensor fabricated in a 0.18mum 1P3M process is described. A zigzag-shaped 1.75T/pixel architecture and a 10b counter-type column parallel ADC enables 2.5times2.5mum2 pixels. The resulting pixel has 38% fill factor, 12ke-/lux-s, and random noise of 7e-rms. A 10b parallel LVDS interface enables data rates of up to 4.32Gb/s with 216MHz DDR. Full frame and 2times2 binning modes are interchangeable without an extra invalid frame

A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change

A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS image sensor fabricated in a 0.18-mum single-poly triple-metal (1P3M) process is described. A zigzag-shaped 1.75 T/pixel architecture and a 10-bit counter-type column parallel ADC enables 2.5times2.5 mum2 pixels. The resulting pixel has 38% fill factor and 12ke-/lux.s sensibility. In addition, full frame and 2times2 binning modes are interchangeable without an extra invalid frame

6.1 A 1/1.7-inch 20Mpixel Back-illuminated stacked CMOS image sensor for new imaging applications

The demand for low-noise (for capturing a clear image in low-light conditions), high-speed (for slow-motion applications and reducing rolling shutter distortion) and high-resolution (for formats beyond 4K) CMOS image sensors is still increasing. In addition, the emerging camcorder market typified by handsfree devices requires the simultaneous capture of still and moving images. To improve noise performance, a method of pseudo-multiple sampling has been proposed [1]. However, the noise reduction effect is insufficient due to the non-uniformity of the CDS period. For high frame rates, multichannel and high-data-rate interfaces have been reported [2-4]. For simultaneous capture of still and moving images, a seamless mode change has been shown [5], but it is necessary to convert a still image (full pixel data) to a moving image (2×2 binning data) by an external DSP.