Yoshihiro Takemae

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international solid-state circuits conference | 1985

A 1Mb DRAM with 3-dimensional stacked capacitor cells

Yoshihiro Takemae; T. Ema; M. Nakano; Fumio Baba; T. Yabu; Kiyoshi Miyasaka; K. Shirai

pads in the center of the chip, permit assembly within a 300mil 18 pin plastic DIP and 300mil26 pin plastic Small Outline J-lead package (SOJ). The cell structure is shown in Figure 1. First layer polycide forms the wordline. The second layer poly-Si, which forms the storage node, is extended over its own wordline and the next wordline. The third layer poly-Si, which forms the cell plate, is spread over the second layer poly-Si. The cell capacitor is formed between the second and third layer poly-Si. Bitline is formed by AI. Since the capacitor is formed over the wordlines, the address The chip layout, with peripheral circuitry and some of the

Archive | 1993

Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

Masao Taguchi; Satoshi Eto; Yoshihiro Takemae; Hiroshi Yoshioka; Makoto Koga

Archive | 1994

Semiconductor memory having a plurality of banks usable in a plurality of bank configurations

Hirohiko Mochizuki; Yoshihiro Takemae; Yukinori Kodama; Makoto Yanagisawa; Katsumi Shigenobu

Microelectronics Reliability | 1989

Semiconductor memory device having error correction function and incorporating redundancy configuration

Yoshihiro Takemae

Archive | 1986

Semiconductor memory device formed of a SOI-type transistor and a capacitor

Yoshihiro Takemae

Archive | 1997

Semiconductor memory system using a clock-synchronous semiconductor device and semiconductor memory device for use in the same

Hiroyoshi Tomita; Yoshihiro Takemae

Archive | 1983

Semiconductor memory device having stacked capacitor-type memory cells

Yoshihiro Takemae; Tomio Nakano; Kimiaki Sato

Archive | 1985

Random access memory device formed on a semiconductor substrate having an array of memory cells divided in sub-arrays

Yoshihiro Takemae

Archive | 1980

Semiconductor devices having fuses

Hirohiko Mochizuki; Masao Nakano; Fumio Baba; Tomio Nakano; Yoshihiro Takemae

Archive | 2001

Semiconductor memory device capable of reducing power consumption in self-refresh operation

Yoshihiro Takemae; Yasurou Matsuzaki

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Fujitsu

Archive Network Publication Hotspot Collaboration

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Latest external collaboration on country level. Dive into details by clicking on the dots.

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Dive into the research topics where Yoshihiro Takemae is active.

Publication

Featured researches published by Yoshihiro Takemae.

A 1Mb DRAM with 3-dimensional stacked capacitor cells

Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

Semiconductor memory having a plurality of banks usable in a plurality of bank configurations

Semiconductor memory device having error correction function and incorporating redundancy configuration

Semiconductor memory device formed of a SOI-type transistor and a capacitor

Semiconductor memory system using a clock-synchronous semiconductor device and semiconductor memory device for use in the same

Semiconductor memory device having stacked capacitor-type memory cells

Random access memory device formed on a semiconductor substrate having an array of memory cells divided in sub-arrays

Semiconductor devices having fuses

Semiconductor memory device capable of reducing power consumption in self-refresh operation

Collaboration

Dive into the Yoshihiro Takemae's collaboration.