Yoshikazu Furuta

Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel

A polycrystalline-silicon thin-film transistor (TFT), with a single grain boundary (GB) present in the channel, is simulated using two-dimensional numerical simulation, which includes a model of deep trap states at GBs. It is observed that the potential barrier resulting from a GB in the channel acts to suppress current flowing through the channel when the barrier height is greater than the thermal voltage. The conduction mechanism in the subthreshold regime is clarified. The turn-on characteristics of the device are controlled primarily by gate-induced grain barrier lowering as opposed to modulation of carriers in the channel by the gate voltage. In the negative bias region it is found that suppression of the off current is aided by the GB potential barrier. Scaling of the various geometrical parameters of the device are investigated. Improved subthreshold characteristics, compared to an equivalent silicon-on-insulator (SOI) structure, are found for aggressively scaled devices, due to the presence of a GB in the channel.

Reduction of grain-boundary potential barrier height in polycrystalline silicon with hot H2O vapor annealing probed using point-contact devices

The effects of hot H2O-vapor annealing were investigated on local carrier transport properties over a few grain boundaries in polycrystalline silicon. It shows that hot H2O-vapor annealing effectively reduces grain-boundary dangling bonds and the potential barrier height. In addition, it narrows the distribution of the barrier height value significantly. These effects are thought to originate from oxidation in the vicinity of the film surface, and from hydrogenation in the deeper region. Our results suggest that H2O annealing can improve the carrier transport properties by opening up shorter percolation paths and by increasing the effective carrier mobility and density.

Carrier Transport across a Few Grain Boundaries in Highly Doped Polycrystalline Silicon

We have fabricated nanometer-scale point-contact devices in 50-nm-thick poly-Si films with a grain size of from 150 nm to 20 nm. Both linear and nonlinear Ids-Vds characteristics were observed in these devices, corresponding to a channel without a grain boundary (GB) and that with a single or a few GBs, respectively. The temperature dependence of resistivity indicated that the effective potential barrier height qVB of the GBs for the devices which show the nonlinear Ids-Vds characteristics ranges from 30 meV to 80 meV. We discussed percolation conduction of electrons through a few GBs due to nonuniform GB properties in heavily doped poly-Si films.

Characterization of Tunnel Barriers in Polycrystalline Silicon Point-Contact Single-Electron Transistors

Potential barrier properties of grain boundaries in polycrystalline silicon have been studied using nanometer-scale point-contact transistors. The devices, with channel length and width ranging from 30 nm to 50 nm, were fabricated in a 50-nm-thick film. We found that grain boundaries oxidized at 1000°C acted as tunneling barriers, resulting in the appearance of single-electron charging effects. However, potential barrier heights estimated for oxidized grain boundaries are still low, less than 90 meV, and barrier thickness is as large as ~4 nm. The grain boundary oxides appear to be silicon sub-oxides which are formed by oxygen diffusion into grain boundaries.

Single-Electron Charging Phenomena in Nano/Polycrystalline Silicon Point Contact Transistors

This paper gives a review of our recent work investigating the physics of single-electron charging phenomena in nano/polycrystalline silicon nanostructures. We first provide a short overview on the research of silicon-based single-electron devices from the last decade. Various single-electron transistor structures are compared in terms of control of electron islands and tunnel barriers. We then study the single-electron charging phenomena in nano/polycrystalline silicon nanostructures. A novel point-contact transistor is introduced, which features an extremely short and narrow nano/poly-Si nanowire as the transistor’s channel. This structure is suitable for studying how a grain smaller than 10 nm in size and a discrete grain boundary work as a charging island and a tunnel barrier, respectively. The relationships between structural and electrical parameters of grains/grain-boundaries and the resulting Coulomb blockade characteristics for the point contact transistors are investigated by applying various passivation processes. Finally, optimisation of grain and grain-boundary structures is discussed for improving the Coulomb blockade characteristics and realizing nano/poly-Si single-electron transistors operating at room temperature. Introduction Over the last few decades, the performance of VLSI circuits has been improved steadily by scaling down device dimensions. In dynamic random access memories (DRAMs), for instance, the amount of charge stored per memory cell has been decreased with reduction of the cell area. After the 1 Mbit generation, however, it has become increasingly difficult to keep up such a continuous decrease in the stored charge per bit because the signal becomes less immune to leakage current, internal noise, and soft errors. In microprocessors, power consumption per one MOS transistor has also been reduced due both to miniaturisation and to improved operation conditions. Nevertheless, the total power consumption per microprocessor has gradually been increasing as the number of MOS transistors per chip increases, and the number of electrons used to switch one MOS transistor on and off needs to be reduced further to counter this trend. However, when the number of electrons becomes less than 1000, inherent charge fluctuations cause unacceptable statistical variations in the subthreshold characteristics of the MOS transistors. For both memory and logic applications, how to guarantee future ‘scalability’ of the devices is a key issue, along with a reduction of the number of electrons. Singleand few-electron devices are expected to overcome these issues by introducing the Coulomb blockade (CB) effect [1],[2] as a new principle for the controlled transfer of a small number of electrons. A key building block for singleand fewelectron devices are the double tunnel junction (DTJ) and multiple tunnel junction (MTJ) structures shown in Figs. 1(a) and (b), which are composed of a series of islands with tunnel barriers between them. When a single electron enters onto the island, the charging energy EC of the island increases, and the transfer of even one electron is strongly suppressed (Coulomb blockade) if the charging energy is higher than the thermal energy kBT. From the device-engineering point of view, the MTJ is more preferable than the simple DTJ since it reduces co-tunnelling [3], which generally leads to unfavourable leakage current. Also the MTJ structure is robust against offset charge effects [4][5], which vary the Coulomb gap and even may break the CB. In general, the tunnel junction (TJ) should meet the following two requirements to show the CB effects at a temperature T: (a) (b) conductor island Fig.1: (a) Double tunnel junction and (b) multiple tunnel junction. Rt ≫ RQ = h/e = 25.6 kΩ (1) EC = e/2CΣ ≫ kBT (2) to avoid quantum and thermal smearing of the electronic states confined in the islands. In Eqs. (1) and (2) RQ is the quantum resistance (≡ h/e), and Rt and CΣ are the total tunnel resistance of the TJ and total capacitance of the electron islands, respectively. A number of fabrication methods for DTJs and MTJs have been reported. These structures may be classified into two groups in terms of the manner of formation of nanoscale electron islands: patterned electron islands and naturally formed ones. A silicon-based patterned island structure has been realized by using a pattern-dependent oxidation (PADOX) technique [6]. This technique utilizes faster oxidation caused by stress at the pattern edge, and a DTJ is formed at the both ends of a Si nanowire (NW). This technique has achieved a single electron island with a lateral size of less than 10 nm. An alternative approach is to use an AFM-based oxidation technique [7]. A NbO2 DTJ was defined on a Nb NW resulting in a Nb single island with a lateral dimension of a few nm. A step edge cut off (SECO) technique [8] has also been reported to form a metallic MTJ structure. Table Naturally formed structures exploit various kinds of local disorder in nanometer-scale structures to form the DTJ or MTJ. In a heavily doped Si NW [9] with a few tens of nanometers in width, randomly distributed dopant atoms cause potential fluctuations, and a linear chain of electron islands are formed when a negative gate bias is applied to a gate electrode placed adjacent to the NW [10]. This is a fairly simple structure and has often been used for making CB memory [11][12] and logic [13] devices. However, the CB oscillation can usually be observed Naturally-formed Patterned Controllability of dot size Controllability of dot position Controllability of tunnel barrier thickness Compatibility with Si-ULSI Controllability of tunnel barrier height Random dopant induced Roughness induced Defect induced

Carrier Transport in Ultra-Thin Nano/Polycrystalline Silicon Films and Nanowires

Carrier transport was investigated in two different types of ultra-thin silicon films, polycrystalline silicon (poly-Si) films with large grains > 20 nm in size and hydrogenated nanocrystalline silicon (nc-Si:H) films with grains 4 nm – 8 nm in size. It was found that there were local non-uniformities in grain boundary potential barriers in both types of films. Single-electron charging effects were observed in 30 nm × 30 nm nanowires fabricated in 30 nm-thick nc-Si:H films, where the electrons were confined in crystalline silicon grains encapsulated by amorphous silicon. In contrast, the poly-Si nanowires of similar dimensions showed thermionic emission over the grain boundary potential barriers formed by carrier trapping in grain boundary defects.

Tunnel Barrier Properties of Polycrystalline-Si Single-Electron Transistor

This paper discusses the electrical and structural properties of tunnel barriers in polycrystalline-Si singleelectron transistors. A novel point-contact device is introduced, which features an extremely short poly-Si nanowire as a channel. This structure suits for studying how a few discrete grain boundaries work as tunnel junctions. The relationship between tunnel barrier parameters and Coulomb blockade characteristics is investigated by comparing as-prepared and oxidized devices.