Yoshikazu Miyanaga

Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system

This paper describes a scalable architecture for real-time speech recognizers based on word hidden Markov models (HMMs) that provide high recognition accuracy for word recognition tasks. However, the size of their recognition vocabulary is small because its extremely high computational costs cause long processing times. To achieve high-speed operations, we developed a VLSI system that has a scalable architecture. The architecture effectively uses parallel computations on the word HMM structure. It can reduce processing time and/or extend the word vocabulary. To explore the practicality of our architecture, we designed and evaluated a complete system recognizer, including speech analysis and noise robustness parts, on a 0.18-/spl mu/m CMOS standard cell library and field-programmable gate array. In the CMOS standard-cell implementation, the total processing time is 56.9 /spl mu/s/word at an operating frequency of 80 MHz in a single system. The recognizer gives a real-time response using an 800-word vocabulary.

Cepstral gain normalization for noise robust speech recognition

The paper describes a robust speech recognition technique which normalizes cepstral gains in order to remove effects of additive noise. We assume that the effects can be expressed by an approximate model which consists of gain and DC components in log-spectrum. Accordingly, we propose cepstral gain normalization (CGN) which normalizes the gains by means of calculating maximum and minimum values of cepstral coefficients in speech frames. The proposed method can extract noise robust features without a priori knowledge and environmental adaptation because it is applied to both training and testing data. We have evaluated recognition performance under noisy environments using the Noisex-92 database and a 100 Japanese city names task. The CGN provides improvements of recognition accuracy at various SNRs compared with combinations of conventional methods.

Adaptive identification of a time-varying ARMA speech model

We propose an adaptive algorithm to estimate time-varying ARMA parameters for speech signals. It estimates both input excitations and underlying system parameters. The proposed algorithm is an extended form of the Kalman filter algorithm. We assume the input is either a white Gaussian process or a pseudoperiodical pulse-train as commonly adopted in LPC processing. The time variation of parameters is monitored by a likelihood function. In order to estimate optimal parameters in a small amount of data, AR and MA orders of an estimator are set to be higher than those of a true system. Parsimonious ARMA parameters are calculated from parameters obtained by the high-order ARMA model. Examples of synthetic and real speech sounds are given to demonstrate the tracking ability of this algorithm.

VLSI Implementation of a 4×4 MIMO-OFDM transceiver with an 80-MHz channel bandwidth

VLSI Implementation for a 4×4 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) transceiver is described that targets 1-Gbps data transmission for next-generation wireless LAN systems. The IEEE802.11 Very High Throughput (VHT) Study Group concluded that a signal bandwidth of more than 80 MHz is needed to achieve 1-Gbps throughput in the MAC layer. The proposed architecture is suitable for VLSI implementation that meets this specification and enables real-time processing in a 4×4 MIMO-OFDM configuration. It incorporates a minimum meansquare error (MMSE) MIMO detector that drastically shortens processing latency. Evaluation of a MIMO-OFDM transceiver implemented in CMOS with 128, 256, or 512 OFDM subcarriers showed that the power dissipation ranged from 451 to 577 mW.

Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator

We present a low power architecture that dynamically controls wordlengths in a wireless OFDM demodulator. Finding the optimum wordlength for digital circuit systems is difficult because the trade-off between the hardware cost and system performance is not conclusive. Actual circuit systems have large wordlengths at the circuit design level to avoid calculation errors caused by a lack of dynamic range. This indicates that power dissipation can still be reduced under better conditions. We propose a tunable wordlength architecture that dynamically changes its own wordlength according to the communication environment. The proposed OFDM demodulator measures error vector magnitudes (EVMs) from de-modulated signals and tunes the wordlength to satisfy the required quality of communication by monitoring the EVM performance. The demodulator can reduce dissipated energy by a maximum of 32 and 24% in AWGN and multipath fading channels.

A speech analysis algorithm which eliminates the influence of pitch using the model reference adaptive system

A new adaptive algorithm based upon a least square criterion with a weighting factor is presented and shown to be quite useful for estimating ARMA parameters together with input in speech analysis. The estimator of both the input pulse train for voiced speech and the input white noise for unvoiced speech are easily obtained from the prediction errors by using this new adaptive algorithm. When these estimated inputs are used as the input of the model to be estimated, the influence of the pitch can be eliminated from the estimated ARMA parameters. By using this method the accuracy of formant and antiformant estimators is shown experimentally in comparison with LPC and cepstrum estimators.

MIMO Zero-Forcing Detection Analysis for Correlated and Estimated Rician Fading

Experimental modeling of wireless fading channels performed by the WINNER II project has been shown to fit a Rician rather than Rayleigh distribution, the latter being assumed in many analytical studies of multiple-input-multiple-output (MIMO) communication systems. Unfortunately, a Rician MIMO channel matrix has a nonzero mean (i.e., specular component) that yields, for the matrix product that determines the MIMO performance, a noncentral Wishart distribution that is difficult to analyze. Previously, the noncentral Wishart distribution has been approximated, based on a first-order-moment fit, by a central Wishart distribution and used to derive average error probability (AEP) expressions for zero-forcing (ZF) detection. We first reveal that this approximation and the MIMO performance evaluation tools derived from it may be reliable only for rank-one specular matrices. We then exploit this approximation to derive an AEP expression for a lesser known, yet optimal, MIMO ZF approach that, unlike the conventional approach, accounts for channel estimation accuracy through the channel statistics. After validating this AEP expression for the rank-one case, it is shown that the ZF performance averaged over realistic (i.e., WINNER II) distributions of the Rician K-factor and azimuth spread (AS) can be much worse than that for the average K and AS. Finally, through simulations, it is shown that the optimal detection approach can substantially outperform the conventional approach for ZF for full-rank specular matrices, as well as for minimum mean square error detection for both rank-one and full-rank specular matrices.

OTA-based high frequency CMOS multiplier and squaring circuit

A gigahertz analog multiplier based on OTA and squaring is proposed. The multiplier has gigahertz frequency response is suitable to use in communication system. The circuit is based on 0.18 μm CMOS technology simulated using PSPICE level 7. This technique provides; wide dynamic range, GHz-bandwidth response and low power consumption. The proposed circuit has been simulated with PSPICE and achieved −3dB bandwidth of 3.96GHz. The total power dissipation is 0.588mW with ±1V power supply voltages..

A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver

This paper presents a VLSI architecture of MMSE detection in a 4 x 4 MIMO-OFDM receiver. Packet-based MIMO- OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We adopt Strassens algorithms of matrix inversion and multiplication to circuit design in the MMSE detection. The complete pipelined architecture achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.issue.

Parallel and adaptive clustering method suitable for a VLSI system

The authors propose a two-functional network in which adaptive networks are implemented for sophisticated recognition and clustering. In the first subnetwork, self-organized clustering is realized. The clustering is based on Mahalanobis distance. The result of the first subnetwork becomes a vector of similarity values between a given input pattern and all patterns of cluster nodes. The second subnetwork consists of nodes associated with specific labels. All connections between the label nodes of the second functional network and the cluster nodes of the first functional network are determined by supervised learning. Every calculation is executed in parallel and pipelined forms. In addition, the proposed network is experimentally shown to provide good performance. In particular, it is shown that handwritten letters can be accurately recognized by using this network.<<ETX>>