Yoshimitsu Yamauchi

A 5 V-only virtual ground flash cell with an auxiliary gate for high density and high speed application

A 5 V-only virtual ground flash EEPROM cell with an auxiliary gate is proposed for high-density and high-speed application. The virtual ground auxiliary gate structure achieves a cell area of 2.59 mu m/sup 2/ with a 0.5- mu m technology and enables a fast programming of less than 1 mu s with a drain voltage of 5 V. It also provides a read-out current higher than 100 mu A and a soft-write lifetime greater than 10 years in read operation. The cell is suitable for high-density flash memories beyond 16 M bits.<<ETX>>

A new cell structure for sub-quarter micron high density flash memory

A new cell structure named ACT (Asymmetrical Contactless Transistor) is proposed for high density data storage applications which require low voltage, low power consumption and fast program/erase. The ACT cell with a lightly doped source and heavily doped drain realizes a simple virtual ground array using the Fowler-Nordheim (FN) tunneling mechanism for both program and erase. A self-aligned floating-gate wing technology is introduced to increase gate coupling ratio in word-line direction without sacrificing cell area. A cell area as small as 0.39 /spl mu/m/sup 2/ with a coupling ratio of 0.55 is obtained using 0.3 /spl mu/m process technology. The low programming current of the ACT cell enables multiple programming to be used and thus it is possible to achieve fast programming (<1 /spl mu/s/byte) with a low single supply voltage (<3 V). A good disturb immunity in program, erase and read modes is also obtained.

Inherent memory effects in ZnS:Mn thin film EL devices

Remarkable hysteresis were found to excist in a thin film multilayer EL device consisting of a ZnS:Mn active layer sandwiched between a pair of Y 2 )0 3 , insulating layers. Due to its particular construction, hysteresis was observed between the brightness vs. amplitude of the exciting alternating voltage, which is instrumental to realizing the memory function. Electrical Writing and Erasing are possible by the amplitude modulation of the sustaining voltage. The typical memory margin observed here is about 10 to 30 volts(rms) under operating voltage of 170 to 280 volts(rms) with frequency of 1 to 5 kHz. Gray scale display as well as Optical Writing are possible.

43.1: A Novel Multi‐level Memory in Pixel Technology for Ultra Low Power LTPS TFT‐LCD

A Novel multi-level memory in pixel technology is proposed for ultra low power TFT-LCD, which can realize the multi-color using the analog voltage grey-scale method. This technology is successfully implemented into the transflective 4 grey-scale (64 colors), 3.17 inch HVGA panel with low power of 300uW and high quality of image.

A versatile stacked storage capacitor on FLOTOX cell for megabit NVRAM applications

A versatile stacked storage capacitor on FLOTOX (SCF) cell is proposed for full featured megabit nonvolatile DRAMs (dynamic RAMs). The SCF cell structure achieves a cell area of 35.02 mu m/sup 2/ with 0.8- mu m features and permits an innovative flash store/recall (DRAM to EEPROM/EEPROM to DRAM) operation that does not disturb the original data in DRAM or EEPROM. This store operation is completed in less than 10 ms and store endurance for a single cell is greater than 10/sup 6/ cycles. In addition, data retention time sufficient for megabit DRAMs (greater than 10 s at RT) is obtained by use of a stacked capacitor structure.<<ETX>>

A novel pixel memory using integrated voltage-loss-compensation (VLC) circuit for ultra-low-power TFT-LCDs

— A novel pixel memory using an integrated voltage-loss-compensation (VLC) circuit has been proposed for ultra-low-power TFT-LCDs, which can increase the number of gray-scale levels for a single subpixel using an analog voltage gray-scale technique. The new pixel with a VLC circuit is integrated under a small reflective electrode in a high-transmissive aperture-ratio (39%) 3.17-in. HVGA transflective panel by using a standard low-temperature-polysilicon process based on 1.5-μm rules. No additional process steps are required. The VLC circuit in each pixel enables simultaneous refresh with a very small change in voltage, resulting in a two-orders-of-magnitude reduction in circuit power for a 64-color image display. The advanced transflective TFT-LCD using the newly proposed pixel can display high-quality multi-color images anytime and anywhere, due to its low power consumption and good outdoor readability.

A Novel Program and Read Architecture for Contact-Less Virtual Ground NOR Flash Memory for High Density Application

We have successfully developed multilevel (MLC) contact-less virtual ground array (VGA-NOR) flash memory. Sequential program from the source side edge cell of each segment and 32cells unit program with data buffer enable to cancel the Vt interference. Sense amplifier (SA) assist equalize-sensing (SAES) is implemented for high accuracy sensing operation

A Novel Source-Side Injection Split-Gate Flash Cell Technology for High Density Low Voltage Applications

The conventional single gate cell makes it difficult to realize both single power supply programming due to its low programmability and low voltage read-out due to its overerase structure. Recently several studies U l,[2] on source-side-injection Flash cells have been reported to improve the above-mentioned issues without increasing the cell area. However, they suffer from the high resistance of the side-wall select gate working as a wordline[1] or overerase issues[2]. This paper describes a sos split-gate cell acceptable for SV-only or 3.3V-only high density Flash memories.

Red electro-luminescence from ZnS:Mn-F thin film

Thin film EL device made of ZnS:TbF 3 , Mn by means of electron beam evaporation yield red light (peak wave length 7000 A) at a brightness of 60 Fl. The color of the light varied from orange to red according to the concentration ratio of TbF 3 to Mn. Two emission bands were observed, namely at 5850 A and 7000 A. Since the orange band is obviously due to the localized center of Mn2+, our experimental results support that the red emission band is due to the localized center of Mn2+, our experimental results support that the red emission bands is due to the localized center of Mn-F.

A pure metal polycide metal‐oxide‐semiconductor gate technology

A pure metal (molybdenum) polycide MOS gate with a trilevel gate structure (Mo/thin MoSix/polysilicon) has been studied and different MoSix thicknesses ranging from 0 to 40 nm were examined. Even at high temperatures there is no interfacial reaction between the Mo and polysilicon nor any deterioration of the dielectric strength of MOS capacitors when this trilevel gate structure is used with an inter‐MoSix layer thickness of around 15 nm. This MOS structure offers stable MOS characteristics and low resistive molybdenum interconnections in VLSI process technology.