Yoshinari Kumaki
Toshiba
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Featured researches published by Yoshinari Kumaki.
vehicular technology conference | 1996
Mutsumu Serizawa; K. Nonin; Eiji Kamagata; Nobuyasu Nakajima; Keiji Tsunoda; Yoshinari Kumaki
SDL-Net (Super high speed DownLink Network) is proposed as a wireless access link to a broadband multimedia network, and its basic features are described. In the SDL-Net, the transmission data rate in downlink is 30 to 300 times faster than the transmission data rate in uplink. With this asymmetric architecture, most of multimedia personal communication services are realized through hand-held portable multimedia terminals. The SDL-Net is economically constructed by additionally installing high speed downlink transmitters in existing narrowband personal communication networks. By combining high speed downlink with narrowband links, both seamless CBR services such as voice communication and spot beam VBR services such as electronic publishing are realized.
IEEE Journal of Solid-state Circuits | 1991
Kenji Sakaue; Yasuro Shobatake; Masahiko Motoyama; Yoshinari Kumaki; Satoru Takatsuka; Shigeru Tanaka; Hiroyuki Hara; Kouji Matsuda; Shuji Kitaoka; Makoto Noda; Y. Niitsu; M. Norishima; Hiroshi Momose; K. Maeguchi; Manabu Ishibe; Shoichi Shimizu; Toshikazu Kodama
An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8- mu m BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical). >
Archive | 1998
Yoshinari Kumaki; Keiji Tsunoda; Shigeo Matsuzawa; Noriyasu Kato; Osamu Moriya; Toshio Okamoto
Archive | 2000
Atsushi Inoue; Eiji Kamagata; Noriyasu Kato; Naohisa Shibuya; Yoshinari Kumaki; Yasuro Shobatake
Archive | 2002
Atsushi Inoue; Yoshinari Kumaki
Archive | 1991
Yasuro Shobatake; Emiko Shobatake; Takashi Kamitake; Kazuhiko Hanawa; Kazuaki Iwamura; Yoshinari Kumaki
Archive | 1999
Atsushi Inoue; Masahiro Ishiyama; Atsushi Fukumoto; Yoshiyuki Tsuda; Toshio Okamoto; Masataka Goto; Yoshinari Kumaki
Archive | 1990
Yasuro Syobatake; Yoshinari Kumaki
Archive | 1996
Katsuya Nounin; Takashi Wakutsu; Nobuyasu Nakajima; Koji Ogura; Mutsumu Serizawa; Osamu Moriya; Tsutomu Sugawara; Eiji Kamagata; Yoshinari Kumaki
Archive | 1996
Nobuyasu Nakajima; Koji Ogura; Mutsumu Serizawa; Yoshinari Kumaki; Katsuya Nounin; Eiji Kamagata; Takashi Wakutsu; Tsutomu Sugawara