Yoshinori Matsuno

High-efficient operation of large-area (100 cm2) thin film polycrystalline silicon solar cell based on SOI structure

Abstract High-efficient operation of a large-area thin film polycrystalline Si solar cell with a novel structure based on a silicon on insulator (SOI) structure prepared by zone-melting recrystallization (ZMR) is reported. The (100) crystal orientation area over 90% has successfully been obtained by controlling the ZMR conditions, which allowed to form a uniform random pyramidal structure at the cell surface. The effect of hydrogen passivation has also been investigated for further improvement of the cell characteristics. By employing a light trapping structure (textured surface) and hydrogen passivation, an efficiency of 14.22% was obtained for a practical 100 cm 2 size.

Light Trapping for Thin-Film Silicon Solar Cells Fabricated on Insulator

We have developed a new solar cell using thin-film silicon supported by a silicon substrate etched in a grid form. The light-trapping structures of this cell have been studied by considering rear surface light reflections, electrical power loss and mechanical strength. High rear reflectance can be obtained by employing a multi-layer rear electrode. The pattern of the rear substrate is designed to provide sufficient mechanical strength and to minimize the electrical power loss, taking account of the current flow path. A conversion efficiency of 14.2% for a practical size of 10×10 cm2 is obtained by applying these calculated parameters using a single-crystal silicon substrate.

4H-SiC Power Metal?Oxide?Semiconductor Field Effect Transistors and Schottky Barrier Diodes of 1.7 kV Rating

4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) and Schottky barrier diodes (SBDs) of 10 A/1.7 kV rating were fabricated and characterized. Suitable design of a drift layer and a junction termination realized stable avalanche breakdown of 1.8 kV. Relatively low on-resistances of 8.3 mΩ cm2 for the MOSFET and 2.2 mΩ cm2 for the SBD were successfully recorded. Temperature dependence of the static characteristics of the SBD showed positive temperature coefficient in both the avalanche breakdown voltage and the differential on-resistance. The MOSFET and SBD were assembled into an SiC module. Its dynamic characterization revealed that the switching loss reduction in the SiC module was as much as 86% in comparison with that of the conventional Si counterpart under a moderate switching condition.

Distribution of Forward Voltage of SiC Schottky Barrier Diode Using Ti Sintering Process

The forward current density-voltage (JF-VF) characteristics of SiC Schottky barrier diodes (SBDs) with an epilayer thickness between 9.6 and 10 μm and donor concentration (ND) ranging from 4.0x1015 to 5.7x1015 cm-3 was evaluated. It was found that the Schottky barrier height (Φb) can be stabilized by Ti sintering process and the forward current (IF) abruptly rises at the same knee voltage for all samples. On the other hand, the on-resistance (Ron) and VF were dispersed. The instability corresponds to the values calculated by the dispersion of ND, substrate resistivity and substrate thickness.

Numerical Evaluation of Forward Voltage in SiC Pin Diode with Non-Ohmic Current Component in Contact to p-Type Layer

Forward voltage of SiC pin diodes is evaluated by device simulation, where a p-type contact is described by Schottky barrier to a p-type surface region. The contact resistance is calculated from the comparison to I-V characteristic of Schottky structure to a p-SiC layer with a sufficiently low Schottky barrier height. Even in the relatively low contact resistance rc of 10-4 Wcm2, non-ohmic current component is observed in Schottky structure to p-SiC and the increase of forward voltage of pin diodes is fairly small. Forward voltage of pin diodes increases in the pin diodes with contact resistance rc over 10-4 Wcm2. The same behavior is also observed irrespective of a time constant of carriers, and doping concentration and thickness of a drift layer.