Yoshitoshi Kunieda
Wakayama University
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Featured researches published by Yoshitoshi Kunieda.
ieee international conference on high performance computing data and analytics | 1999
Mariko Sasakura; Kazuki Joe; Yoshitoshi Kunieda; Keijiro Araki
For effective use of parallelizing compilers, an interactive environment which allows users to find more parallelism is needed. As the first step towards building such an environment, we have developed a program visualization system named NaraView. In this paper, we describe two visualization methods in NaraView. One is Program Structure View which illustrates the hierarchical loop structure of a given program and suggests which parts of the program can be parallelized. Another is the Data Dependence View which visualizes each data dependence on every variable or array element which is accessed in a specific loop. By using these views, users can easily understand which part of the program can be parallelized further. We also show several examples to demonstrate the efficiency of these methods.
Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) | 1999
Masami Takata; Yoshitoshi Kunieda; Kazuki Joe
In this paper, we propose several heuristics that improve the branch and bound based program partitioning algorithm proposed by Girkar et al., and evaluate the effectiveness by experiments. The heuristic depends heavily, on the element order of edges of a given task graph. Therefore, it is necessary to sort the edges carefully to make effective use of the heuristic. Different sorting methods are investigated and experimentally evaluated. Approximate solutions that provide a sufficient practical partitioning were obtained using the accelerated heuristic, and execution times and error compared to the optimal solutions decreased considerably by sorting the edges of the task graph.
Innovative Architecture for Future Generation High-Performance Processors and Systems | 1998
Shoichi Saito; Tetsutaro Uehara; Kazuki Joe; Yoshitoshi Kunieda
In order to provide a fully-autosmutic parullelzing compiler with the furiction of both automatic datu partitioning and distribution, we propose a compilercontrolled cache only memory architecture (cc-COMA). The cc-COMA runtime system as based on a softwure-emulated COMA which covers a variety of parallel architectures from NUMA to NOW. The compiler generates both the user code and control code for the emulated cache based on the Entry Consistency model. The runtime system of cc-COMA executes the generated code following the suggestions of the compiler. In this paper we present an outline of what we call the cc-COMA system. Also described is an implementation of the cc-COMA, runtime system for networks of workstations, named Laurasia.
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003 | 2003
Masaaki Mineo; Tetsutaro Uehara; Shoichi Saito; Yoshitoshi Kunieda
Data dependence analysis is essential for automatic parallelizing compilers. Compilers determine the possibility of parallelization on given source programs by using the result from data dependence analysis. Several dependence analysis tests on array data have been already proposed. Each test cannot avoid the trade-off between its analysis speed and exactness of analysis. Among such tests, the Omega test is well known as an exact test for the broader class of index expressions. However, the Omega test algorithm is so complicated that its analysis is very time consuming and it is difficult to implement the Omega test. Therefore, in this paper a new original test is proposed, whose algorithm combines both the Simplex method for linear programming and an exhaustive solution search method. The algorithm, its implementation details, and evaluation applied to concrete numerical programs are also described.
Atmospheric Environment | 1999
T. Uehara; Shoichi Saito; Kazuki Joe; Yoshitoshi Kunieda
We have proposed an approach to build an automatic parallelizing compiler for various parallel computer architectures by providing COMA (Cache-Only Memory Architecture) environment that can be controlled by the compiler. This paper presents the design and implementation of a software DSM (Distributed Shared Memory) system named Laurasia. It also describes a Low-Costs Communication module named Win which is developed to accelerate the performance of Laurasia. Laurasia is designed to run on a cluster of UNIX Workstations or PCs, and Wind is built in a Linus kernel to eliminate context switches between the kernel and the user process.
ieee international conference on high performance computing data and analytics | 1997
Tetsutaro Uehara; Yoshitoshi Kunieda; Takao Tsuda
This paper descrives the design and implementation of the automatic vectorizing and paralellizing compiler named V-Pascal Version 3. The compiler is designed as a workbench on which various vectorizing and parallelizing techniques are evaluated. Now this compiler has the ability of vectorizing/parallelizing multiply-nested loops as reduced single loops, vectorizing while-loops and recursive calls, analyzing aliases caused by pointers, detecting dynamic data-structures such as linkedlists and so on. These special techniques can be applied not only for Pascal.
情報処理学会研究報告システム評価(EVA) | 2002
Kazuya Okuno; Satoshi Yokote; Shoichi Saito; Tetsutaro Uehara; Yoshitoshi Kunieda; Akira Fukuda
IPSJ SIG Notes | 2000
Tetsutaro Uehara; Shoichi Saito; Kazuki Joe; Yoshitoshi Kunieda
ieee international conference on high performance computing, data, and analytics | 1992
Takao Tsuda; Yoshitoshi Kunieda
ifip congress | 1986
Takao Tsuda; Yoshitoshi Kunieda