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Proceedings of SPIE - The International Society for Optical Engineering | 1987

Component Labeling Algorithm For Video Rate Processing

Toshiyuki Gotoh; Yoshiyuki Ohta; Masumi Yoshida; Yoshio Shirai

In this paper, we propose a raster scanning algorithm for component labeling, which enables processing under pipeline architecture. In the raster scanning algorithm, labels are provisionally assigned to each pixel of components and, at the same time, the connectivities of labels are detected at first scan. Those labels are classified into groups based on the connectivities. Finally provisional labels are updated using the result of classification and a unique label is assigned to each pixel of components. However, in the conventional algorithm, the classification process needs a vast number of operations. This prevents realizing pipeline processing. We have developed a method of preprocessing to reduce the number of provisional labels, which limits the number of label connectivities. We have also developed a new classification method whose operation is proportionate to only the number of label connectivities itself. We have made experiments with computer simulation to verify this algorithm. The experimental results show that we can process 512 x 512 x 8 bit images at video rate(1/30 sec. per 1 image) when this algorithm is implemented on hardware.


Systems and Computers in Japan | 1990

High-speed algorithm for component labeling

Toshiyuki Gotoh; Yoshiyuki Ohta; Masumi Yoshida; Yoshiaki Shirai

This paper describes a fast labeling algorithm which separates regions lying all over an image based on a pipeline method. In the previous labeling algorithm of raster-scan type, a bottleneck for fast processing was the label classification process to classify temporarily assigned labels based on the connectivity. To cope with this problem, consideration was given to how to reduce the number of connectivities input to the labeling process, and how to make the labeling process efficient. For the problem of the number of connectivities, a method was developed for reducing the number of connectivities due to reshaping of a region, and a fast method for reducing the number of duplicate connectivities by introduction of a dividing process. Also, for the problem of label classification, a label classification method was developed using direct search for connectivities. Moreover, the relationship between the number of provisional labels in the labeling process and the number of connectivities was investigated. As a result, it was shown that the label classification process can be implemented in time proportional to the number of provisional labels and the effectiveness of the algorithm presented here was verified by simulation.


Proceedings of SPIE - The International Society for Optical Engineering | 1989

Video-Rate Labeling Processor

Masatoshi Komeichi; Yoshiyuki Ohta; Toshiyuki Gotoh; Toshiya Mima; Masumi Yoshida

We have developed a component labeling processor amenable to pipelining and video-rate processing. The component labeling is widely used in various fields. However, the conventional algorithms have a problem that the operations rapidly increases as the shape of components becomes complex. This problem prevents us from realizing a high-speed processing. In this paper, we discuss an architecture of this processor and the algorithm for solving the problem. Our processor consists of four kinds of processing units. The pre-processing unit simplifies the shape of components to reduce the number of provisional labels. In the provisional labeling unit, each pixel of components is labeled provisionally using the local connectivity of pixels. The label classification unit classifies the provisional labels by the method of searching the label connectivities. In the label update unit, the provisional label of each pixel is replaced by the new label, and each component has been uniquely labeled. By this configuration, the provisional labels are searched directly according to the connectivities of the labels in time proportional to only the first power of the labels. The experimental results verify that we can process 512 x 512 x 8 bit TV images in pipeline at video-rate using our processor.


Systems and Computers in Japan | 1992

IDATEN: A reconfigurable video-rate color image processing system

Satoshi Naoi; Masatoshi Komeichi; Yoshiyuki Ohta; Tohru Ozaki; Shigeru Sasaki; Toshiyuki Gotoh; Masumi Yoshida

This paper discusses the system IDATEN, which can process color dynamic images at the video rate. The pipeline architecture, which has previously been presented, has a high potential for high-speed image processing. However, a problem in this architecture is the lack of flexibility since processors are connected in cascade. To cope with this problem, the authors have devised a reconfigurable pipeline, where high-speed processors can be connected by a network in a flexible way


Medical Imaging IV: PACS Systems Design and Evaluation | 1990

Prototype of image compression system for medical images

Yukihiro Nakagawa; Toshiyuki Yoshitake; Yoshiyuki Ohta; Toshiyuki Gotoh; Masumi Yoshida

We previously developed an image reconstruction display for reconstructing images compressed by our hybrid compression algorithm. The hybrid algorithm, which improves image quality, applies Discrete Cosine Transform coding (DCT) and Block Truncation Coding (BTC) adaptively to an image, according to its local properties. This reconstruction display receives the compressed data from the host computer through a BMC channel and quickly reconstructs good quality images using a pipeline-based microprocessor. This paper describes a prototype of a system for compression and reconstruction of medical images. It also describes the architecture of the image compression processor, one of the components of the system. This system consists of the image compression processor, a host main-frame computer and reconstruction displays. Under this system, distributed processing in the image compression processor and the image reconstruction displays reduces the load on the host computer, and supplies an environment where the control routines for PACS and the hospital information system (HIS) can co-operate. The compression processor consists of a maximum of four parallel compression units with communication ports. In this architecture, the hybrid algorithm, which includes serial operations, can be processed at high speed by communicating the internal data. In experiments, the compression system proved effective: the compression processor compressed a 1k x 1k image in about 2 seconds using four compression units. The three reconstruction displays showed the image at almost the same time. Display took less than 7 seconds for the compressed image, compared with 28 seconds for the original image.


Archive | 1995

Distance measuring method and a distance measuring apparatus

Shigeru Sasaki; Takashi Toriu; Yoshiyuki Ohta; Masaki Watanabe


Archive | 1994

Mobile communication system having a small base station and equipment for its system

Yoshiyuki Ohta; Toru Itoh


Archive | 2004

Read/write disk drive having read ahead processor which returns a write command, currently being executed, to command queue and executes read command in response to confirmation that there is no overlap

Yoshiyuki Ohta; Katsuhiko Nishikawa


Archive | 2001

Read/write processing device and method for a disk medium

Yoshiyuki Ohta; Katsuhiko Nishikawa


Archive | 2002

Storage unit with improved performance by purging unnecessary data and transferring data with high probability of future hits to a segment buffer

Yoshiyuki Ohta; Katsuhiko Nishikawa

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