Yoshizo Takahashi

Parallel automated wire-routing with a number of competing processors

The purpose of the automated wire routing for VLSI and printed circuit board design is to connect a number of terminal pairs distributed throughout wiring plane with net paths which do not intersect each other. Although maze running and line search are well known algorithms used for this purpose, they need a considerable computing time. To reduce it we have developed a new parallel routing algorithm in which a number of processors compete in wiring different nets independent of each other, and one master processor verifies their results and judges. The master processor also delivers an assignment message to the processors. The efficiency of this algorithm was evaluated on a binary-tree multicomputer and more than 50 times of speedup was obtained when 3000 random nets were routed by using 63 processing elements.

A mechanism for SIMD execution of SPMD programs

Although the SIMD machine is appreciated because of its simple structure leading to the aptness for integration in a VLSI chip, the programming paradigm applicable for this machine is rather poor. If the SPMD program, which is widely used in the MIMD machine, is efficiently executed on the SIMD machine, the versatility of this machine will be very much improved. The key problem of executing a SPMD program on a SIMD machine is the handling of branch instructions and barrier synchronization. To resolve this problem a new branching mechanism which includes the instruction address broadcast, the target address register and the active flag in the processing element, is proposed. The effectiveness of this mechanism is discussed on example programs.

Design of a processing element of a SIMD computer for genetic algorithms

We have been investigating the efficiency of genetic algorithms (GA) for solving for a variety of real problems. During our investigations we have concluded that the large amount of computational time required to find GA based solutions on conventional computers is restrictive. We are therefore developing an innovative new computer architecture, suitable for the solution of large scale problems using GAs. In this paper we introduce the SIMD-GA (Single Instruction stream Multiple Data stream Genetic Algorithm), and discuss its hardware design and implementation. By taking advantage of the recent advances is HDLs (Hardware Description Language) and FPGAs (Field Programmable Gate Array) we have been able to quickly develop and prototype a PE (Processing Element) for a SIMD-GA. This approach allows us to build a cost-effective parallel processing architecture to overcome the problem of the computational time required for traditional sequential GA implementation.

An Enhancement of SIMD Machine for Executing SPMD Programs

While SIMD machine is appraised because of simplicity in structure that fits the massively parallel systems, its programming is limited to depend on inflexible data-parallel paradigm. In order to adapt SIMD machine to more flexible SPMD paradigm for MIMD machine, a new branching mechanism is introduced.

Continuum: A Hybrid Time/Space Communications Paradigm for k-ary n-cubes

Although major advances have been made in improving the performance of interconnection networks for parallel systems, this area continues to be an active avenue of research. This is primarily due to the important role that interconnection network performance plays in determining the overall performance of a system. In this paper we introduce the Continuum communications paradigm, which utilizes multiple, unidirectional, register-insertion buses to provide a hybrid time/space division network. A discussion of the register-insertion bus is presented, along with its extension to k-ary n-cubes. An evaluation of the Continuum paradigm by simulation is given and it is found it to provide an effective model for general inter processor communication.

A distributed operating system for a binary tree multiprocessor

In a massively parallel processing system consisting of hundreds or thousands of processors, the shared data system is unfeasible and the distributed data system seems more promising. Among other architectures the binary tree structure is considered most excellent. Some characteristics of the binary tree multiprocessor, which is named CORAL, are discussed. An operating system for CORAL is designed and named CORALOS. CORALOS is a distributed operating system which has an intensively hierarchical structure. The elementary functions of the operating system are distributed to the groups of OS modules, each one of which consists of a master module and as many slave modules as the processors. Although the slave modules operate independent of each other, they have to respond to the requests delivered from their master module and also report to it when any unusual conditions ocurr. Among the groups of OS modules, the packet handler takes a key role interprocessor communications. Distribution and broadcasting of data are supported by a master packet handler and slave packet handlers. The job program is decomposed and distributed to the processors and is executed as job processes. As an example of the operation of the system, parallel solution of partial differential equation in one dimensional heat conduction problem is illustrated.