Yosinori Watanabe

Metropolis: an integrated electronic system design environment

Today, the design chain lacks adequate support, with most system-level designers using a collection of unlinked tools. The implementation then proceeds with informal techniques involving numerous human-language interactions that create unnecessary and unwanted iterations among groups of designers in different companies or different divisions. The move toward programmable platforms shifts the design implementation task toward embedded software design. When embedded software reaches the complexity typical of todays designs, the risk that the software will not function correctly increases exponentially. The Metropolis project seeks to develop a unified framework that can cope with this challenge. Based on a metamodel with formal semantics that developers can use to capture designs, Metropolis provides an environment for complex electronic-system design that supports simulation, formal analysis, and synthesis.

Synthesis of embedded software using free-choice Petri nets

Software synthesis from a concurrent functional specification is a key problem in the design of embedded systems. A concurrent specification is well-suited for medium-grained partitioning. However, in order to be implemented in software, concurrent tasks need to be scheduled on a shared resource (the processor). The choice of the scheduling policy mainly depends on the specification of the system. For pure dataflow specifications, it is possible to apply a fully static scheduling technique, while for algorithms containing data-dependent control structures, like the if-then-else or while-do constructs, the dynamic behaviour of the system cannot be completely predicted at compile time and some scheduling decisions are to be made at run-time. For such applications we propose a Quasi-Static Scheduling (QSS) algorithm that generates a schedule in which run-time decisions are made only for data-dependent control structures. We use Free Choice Petri Nets (FCPNs), as the underlying model, and define quasi-static schedulability for FCPNs. The proposed algorithm is complete, in that it can solve QSS for any FCPN that is quasi-statically schedulable. Finally, we show how to synthesize from a quasi-static schedule a C code implementation that consists of a set of concurrent tasks.

Task generation and compile-time scheduling for mixed data-control embedded software

The problem of optimal software synthesis for concurrent processes to be implemented on a single processor is addressed. The approach calls for the representation of the concurrent processes with Petri nets that give a theoretical foundation for the scheduling algorithm that sequentializes the concurrent processes and for the code generation step. The approach maximizes the amount of static scheduling to reduce the need of context switch and operating system intervention. Experimental results show the potential of our method to reduce software design time and errors.

Modeling and Designing Heterogeneous Systems

We present the modeling mechanism employed in Metropolis, a design environment for heterogeneous embedded systems, and a design methodology based on the mechanism experimented for wireless communication systems. It is developed to favor the reusability of components in the systems, by decoupling the specification of orthogonal aspects explicitly over a set of abstraction levels. It uses a single model to represent designs specified this way, to which not only simulation but also analysis and synthesis algorithms can be applied relatively easily. The model uses executable code as well as denotational formulas, classes of temporal and predicate logic, so that the right level of details of the design can be defined at each abstraction.

Incremental synthesis for engineering changes

The problem of rectifying design incorrectness due to specification changes as well as design errors of VLSI circuits is formulated and a basic approach using logic synthesis techniques is presented. An efficient approach is presented for rectifying the functional incorrectness by attaching circuitry exterior to the original design. A necessary and sufficient condition for full rectification of the design is provided. It is shown that the proposed approach always succeeds in the rectification of arbitrary combinational circuits. The situation where rectification arises in a practical design process is briefly reviewed.<<ETX>>

Constraints specification at higher levels of abstraction

We are proposing a formalism to express performance constraints at a high level of abstraction. The formalism allows specifying design performance constraints even before all low level details necessary to evaluate them are known. It is based on a solid mathematical foundation, to remove any ambiguity in its interpretation, and yet it allows quite simple and natural specification of many typical constraints. Once the design details are known, the satisfaction of constraints can be checked either by simulation, or by formal techniques like theorem proving, and, in some cases, by automatic model checking.

The maximum set of permissible behaviors for FSM networks

This paper is concerned with the problem of optimizing systems of interacting sequential circuit components. Specifically, we consider how one can find the set of sequential behaviors that can be implemented at a component while preserving the behavior of the total system. This paper proposes a method for computing and representing the complete set of permissible behaviors. We show that the complete set can be computed and represented by a single non-deterministic finite state machine, called the E-machine. The transition relation of the E-machine is obtained by a fixed point computation. The procedure has been implemented and initial experimental results are given.

Heuristic minimization of multiple-valued relations

An approach to minimization that is based on a state-of-the-art paradigm for the two-level minimization of functions is presented. Some special properties of relations, in contrast to functions, which must be carefully considered in realizing a high-quality procedure for solving the minimization problem are clarified. An efficient heuristic method to find an optimal sum-of-products representation for a multiple-valued relation is proposed and implemented in the program GYOCRO. It uses multiple-valued decision diagrams (MDDs) to represent the characteristic functions for the relations. Experimental results are presented and compared with previous exact and heuristic Boolean relation minimizers to demonstrate the effectiveness of the proposed method. >

Concurrent execution semantics and sequential simulation algorithms for the Metropolis meta-model

This paper presents the simulation techniques that are available in Metropolis, an inter-disciplinary research project that develops a design methodology, supported by a comprehensive design environment and tool set, for embedded systems. System behavior is non-deterministic in general, especially in the beginning of the design process, when several key decisions, such as the mapping on an implementation platform, have not yet been made, and thus the traces obtainable by simulation are not unique even under the same input sequence. One may want to visit as many traces as possible for regression tests at the final stage of designs, or may just need one valid trace for a quick validation of the design at an early stage. Our techniques can adapt to these different objectives easily. They are also platform-independent in that simulation using different languages, such as SystemC 2.0, Java, and C++ with a thread library, are possible. This feature is important for co-simulation between designs captured in Metropolis and those that have been already designed in other languages.

Temporofunctional crosstalk noise analysis

Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal transitions in multiple nets by considering both timing and functionality of the signals, and uses it in an analysis procedure to eliminate noise faults that cannot actually happen when such correlations are considered. It uses four-variable Boolean logic to characterize signal transitions in a time interval, and formulates Boolean satisfiability between aggressors and a victim under the min-max delay model for gates. The technique has been successfully applied to commercial ASIC designs and has eliminated up to 35% of delay noise faults reported by a state-of-the-art noise analysis tool.Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal transitions in multiple nets by considering both timing and functionality of the signals, and uses it in an analysis procedure to eliminate noise faults that cannot actually happen when such correlations are considered. It uses four-variable Boolean logic to characterize signal transitions in a time interval, and formulates Boolean satisfiability between aggressors and a victim under the min-max delay model for gates. The technique has been successfully applied to commercial ASIC designs and has eliminated up to 35% of delay noise faults reported by a state-of-the-art noise analysis tool.