Yosuke Ueno

A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture

A wide band, low power, injection-locked oscillator (ILO)-type clock and data recovery (CDR) with high jitter tolerance is implemented in 28 nm CMOS. A robust phase and frequency detection algorithm independently controls ILO free running frequency and clock phase without an external time reference. A wide capture range of -25/+15% enables reference-free frequency acquisition. Jitter tolerance is 0.56 UI at 300 MHz and 1 UI at 120 MHz, with 2 UI locking time after optional calibration. The CDR operates from 1 to 12 Gbps, consuming 11 mW from 0.9 V supply at 12 Gbps for a power efficiency of 0.9 mW/Gbps. A comparison with published results shows a substantial improvement on the trend of wide CDR bandwidth coupled to degraded power efficiency.