Youn-Long Lin

Data path allocation based on bipartite weighted matching

We propose a graph-theoretic approach for the data path allocation problem. We decompose the problem into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian Method [Pap82]. The third subproblem is solved using a greedy method. While previous researches suffer controversy over which one of subproblems (1) and (2) should be done first, we show that, by taking the other into consideration while performing one, equally satisfactory results can be obtained. We have implemented two programs, LYRA and ARYL, to solve the subproblems in different orders, namely, “(1), (2), then (3)” and “(2), (1), then (3)”, respectively. The matching paradigm allows us to take a more global approach toward the problem than previous researches do. For register allocation, our approach is the first one to guarantee minimal usage of registers while being able to take the interconnection cost into account. For all the benchmarks from the literature, both LYRA and ARYL produced designs as good as, if not better than, those by others in very short time. This research has demonstrated that the bipartite weighted matching algorithm is indeed a very good solution for the data path allocation problem.

Recent developments in high-level synthesis

We survey recent developments in high level synthesis technology for VLSI design. The need for higher-level design automation tools are discussed first. We then describe some basic techniques for various subtasks of high-level synthesis. Techniques that have been proposed in the past few years (since 1994) for various subtasks of high-level synthesis are surveyed. We also survey some new synthesis objectives including testability, power efficiency, and reliability.

SILK: a simulated evolution router

The authors present a rip-up-and-rerouter based on a matrix representation scheme and simulated evolution technique for solving detailed routing problems in VLSI layout. The status of the routing region is represented as a matrix. Rip-up and reroute operations are emulated as matrix subtractions and additions, respectively. The quality of a routing result can be measured by a few simple matrix operations on the matrix. A rip-up and reroute switch-box/channel router, called SILK, using a simulated evolution technique has been implemented based on this representation alone. Experimental results showed that SILK, when solving all the benchmarks from the literature, outperformed WEAVER, the most successful switch-box router to date, in both quality and speed aspects. >

Scheduling for functional pipelining and loop winding

We present an algorithm for pipelining loop execution in the presence of loop carried dependences. We optimize both the initiationinterval and the turnaroundtime of a schedule. Given const~aints on the number of functional units and buses, we 6rst determine an initiation interval and then incrementally partition the operations into blocks to fit into the execution windows. A refinement procedure is incorporated to improve the turn around time. The novel feature which differs our approach from others is that the scheduled operations are iteratively moved up and down to accommodate the ready yet unscheduled operations. The algorithm produces very encourageous results.

A near optimal deblocking filter for H.264 advanced video coding

We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant saving in filtering time, local memory usage, and memory traffic. Every 16-16 macroblock requires 192 filtering operations. After a few initialization cycles, our 5-stage pipelined architecture is able to perform one filtering operation per cycle. Compared with some state-of-the-art designs, our architecture delivers the fastest level of performance while using much smaller gate count and memory. We have implemented and integrated the proposed deblocking filter into an H.264 main profile video decoder and verified it with an FPGA prototype

Channel density reduction by routing over the cells

We propose a new approach for reducing the density of a channel by routing some nets (or subnets) over the cells (i.e., outside the channel). Previous research assumed that the more nets being routed over the cells the greater the reduction in the channel density. We show that only the removal of critical nets contributes to the re- duction in the channel density. We divide channel into zones where each zone has a zone density and the removal of any net from a zone will reduce its density by one. In order to reduce the channel density, only certain critical zones need to have their nets routed over the cells. A bipartite graph is used to represent the relationship between nets and zones. The problem is transformed into a constrained covering problem and formulated as an integer linear programming problem. In comparison with previous research, our approach reduces more channel densities while using fewer tracks over the cells. For Deutschs difficult khannel, a previous aiiproach needs 15 tracks over the cells to reduce the channel density by 3 while we need only 5 tracks to achieve the same result . Index Terms-Over-the-cell routing, channel density reduction, stan- dard-cell layout, VLSI routing, integer linear programming.

A transformation-based method for loop folding

We propose a transformation-based scheduling algorithm for the problem given a loop construct, a target initiation interval and a set of resource constraints, schedule the loop in a pipelined fashion such that the iteration time of executing an iteration of the loop is minimized. The iteration time is an important quality measure of a data path design because it affects both storage and control costs. Our algorithm first performs an As Soon As Possible Pipelined (ASAPp) scheduling regardless the resource constraint. It then resolves resource constraint violations by rescheduling some operations. The software system implementing the proposed algorithm, called Theda.Fold, can deal with behavioral loop descriptions that contain chained, multicycle and/or structural pipelined operations as well as those having data dependencies across iteration boundaries. Experiment on a number of benchmarks is reported. >

An effective methodology for functional pipelining

The problem of scheduling a loop in a pipelined fashion such that the iteration time (turnaround time) is minimized, given a loop behavior, a target initiation interval, and resource constraints, is considered. The iteration time is an important quality measure of a data path design because of its direct correlation with both the storage and the control costs. The scheduler starts with performing as-soon-as-possible-pipelined (ASAP/sub p/) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.<<ETX>>

PLS: a scheduler for pipeline synthesis

The authors point out that pipelining is an effective method for optimizing the execution of a loop, especially for digital signal processing (DSP) applications where data enter a circuit regularly. Although throughput and turnaround time are two important optimization criteria, previous work emphasized mainly the throughput. It is shown that the delay time for executing an iteration of a loop has a strong relationship to the cost of the registers and the controller. By minimizing the delay, there is more silicon area to allocate to additional resources, which in turn increases throughput. Forward scheduling and a backward scheduling are iteratively used to achieve this purpose. The algorithm, called PipeLining Scheduler or PLS, can be used to pipeline a loop with or without loop-carried dependencies. Real examples are used to illustrate the method. Experiments on benchmark examples show that considerable improvement over previous approaches is attained. >

LiB: a CMOS cell compiler

An automatic layout generation system, called LiB, for the small-scale integrated (SSI) cells used in CMOS VLSI design, is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a mask layout in CIF. The layout style is a modification of that proposed by T. Uehara, and W. M. van Cleemput (IEEE Trans. Comput., vol.C-30, no.5, p.305-12, 1981). An optimal transistor chaining algorithm has been developed to derive a transistor placement with a minimum number of diffusion separations. To meet the cell height constraint, large transistors are folded into multiple columns algorithmically. The whole cell is divided into five routing regions. Two are on the diffusion island and the others are rectilinear-shaped routing channels. A graph-theoretic method for selecting nets (subnets) for routing on the diffusion island is proposed. A global routing algorithm has been developed to assign the remaining nets to the three rectilinear channels. For the detailed routing SILK, a simulated evolution router, is employed. LiB can be used as a cell library builder or as a subsystem of a random logic module generator. Users can alternate LiBs layout using a symbolic editor. >