Young-Chang Joo

Electromigration-limited reliability of advanced metallization for memory devices

As the design rule for memory devices shrinks, the reliability issue of electromigration (EM) is emerged due 10 the increase of high current density, therefore, the reliability for memory devices can be limited by EM failure of metal lines (Al. Cu. W). But EM reliability with respect to structures of interconnects is still underestimated even though EM behavior for each material has been reported for decades. Therefore, we investigated the kinetics of EM in various metal line and via in memory devices under direct current (DC) stressing because failure of metal interconnects depends not only on metal materials but also on structures of interconnects. Under EM tests, mean time failure of Al with W via was shorter than that of Cu with W via. These results came from abrupt failure behavior due to void nucleation and growth at Al with W via and gradual failure behavior at Cu with W via due to void generation and growth as well as conduction in Ta/TaN. Additionally. Cu with W via showed different behavior compared to Cu with Cu via. It can be explained that the joule heating between W and Cu interface caused lateral void expansion and resistance increases rapidly. And it was observed that W line had the longest lifetime of EM failure but the high resistivity of W should be considered for memory chip design. As the results, we conclude that Al has the weakest reliable property for EM reliability among Al. W and Cu metal lines and W via can affect the degradation of EM reliability. These results mean that reliability of Al and W interconnects beyond nanometer-scale should be improved to guarantee reliability in memory chip. This study could provide the guideline for the optimal materials for interconnects in highly-reliable memory chips.