Young H. Kwark

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization

27.5-percent silicon concentrator solar cells

Recent advances in silicon solar cells using the backside point-contact configuration have been extended resulting in 27.5-percent efficiencies at 10 W/cm2(100 suns, 24°C), making these the most efficient solar cells reported to date. The one-sun efficiencies under an AM1.5 spectrum normalized to 100 mW/cm2are 22 percent at 24°C based on the design area of the concentrator cell. The improvements reported here are largely due to the incorporation of optical light trapping to enhance the absorption of weakly absorbed near bandgap light. These results approach the projected efficiencies for a mature technology which are 23-24 percent at one sun and 29 percent in the 100-350-sun (10-35 W/ cm2) range.

Spiral inductors and transmission lines in silicon technology using copper-damascene interconnects and low-loss substrates

Spiral inductors and different types of transmission lines are fabricated by using copper (Cu)-damascene interconnects and high-resistivity silicon (HRS) or sapphire substrates. The fabrication process is compatible with the concepts of silicon device fabrication. Spiral inductors with 1.4-nH inductance have quality factors (Q) of 30 at 5.2 GHz and 40 at 5.8 GHz for the HRS and the sapphire substrates, respectively. 80-nH inductors have Qs as high as 13. The transmission-line losses are near 4 dB/cm at 10 GHz for microstrips, inverted microstrips, and coplanar lines, which are sufficiently small for maximum line lengths within typical silicon-chip areas. This paper shows that inductors with high Qs for lumped-element designs in the 1-10-GHz range and transmission lines with low losses for distributed-element designs beyond 10 GHz can be made available with the proposed adjustments to commercial silicon technology.

Physics-Based Via and Trace Models for Efficient Link Simulation on Multilayer Structures Up to 40 GHz

Analytical models for vias and traces are presented for simulation of multilayer interconnects at the package and printed circuit board levels. Vias are modeled using an analytical formulation for the parallel-plate impedance and capacitive elements, whereas the trace-via transitions are described by modal decomposition. It is shown that the models can be applied to efficiently simulate a wide range of structures. Different scenarios are analyzed including thru-hole and buried vias, power vias, and coupled traces routed into different layers. By virtue of the modal decomposition, the proposed method is general enough to handle structures with mixed reference planes. For the first time, these models have been validated against full-wave methods and measurements up to 40 GHz. An improvement on the computation speed of at least two orders of magnitude has been observed with respect to full-wave simulations.

Wide band AC power line characterization

This paper presents data characterizing the household AC power line in the 1-60 MHz band. Two types of measurements were performed: transmission and noise sampling. The transmission measurements were done by using the impulse channel sounding method, so both the line attenuation and the delay spread were obtained. The noise measurements include: power line background noise, appliance noise, and noise sampled over a 24 hour period. Statistical characteristics of the delay spread, frequency response and noise can be extracted from the data and used in the design of AC power line based communications systems.

Chip-to-chip optical interconnects

Terabus is based on a silicon-carrier interposer on an organic card containing 48 polymer waveguides. We have demonstrated 4times12 arrays of low power optical transmitters and receivers, operating up to 20 Gb/s and 14 Gb/s per channel respectively

120-Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station

A 120-Gb/s optical link (12 channels at 10 Gb/s/ch for both a transmitter and a receiver) has been demonstrated. The link operated at a bit-error rate of less than 10/sup -12/ with all channels operating and with a total fiber length of 316 m, which comprises 300 m of next-generation (OM-3) multimode fiber (MMF) plus 16 m of standard-grade MMF. This is the first time that a parallel link with this bandwidth at this per-channel rate has ever been demonstrated. For the transmitter, an SiGe laser driver was combined with a GaAs vertical-cavity surface-emitting laser (VCSEL) array. For the receiver, the signal from a GaAs photodiode array was amplified by a 12-channel SiGe receiver integrated circuit. Key to the demonstration were several custom testing tools, most notably a 12-channel pattern generator. The package is very similar to the commercial parallel modules that are available today, but the per-channel bit rate is three times higher than that for the commercial modules. The new modules demonstrate the possibility of extending the parallel-optical module technology that is available today into a distance-bandwidth product regime that is unattainable for copper cables.

40 Gbit/sec circuits built from a 120 GHz f/sub T/ SiGe technology

Product designs for 40 Gbit/sec applications fabricated from SiGe BiCMOS technologies are now becoming available. This paper will briefly discuss technology aspects relating to HBT device operation at high speed, acting to dispel some common misconceptions regarding SiGe HBT technology applicability to 40 Gbit/sec circuits. The high speed portions of the 40 Gbit/sec system are then addressed individually, demonstrating substantial results toward product offerings, on each of the critical high speed elements.

Is 25 Gb/s On-Board Signaling Viable?

What package improvements are required for dense, high-aggregate bandwidth buses running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Hardware-validated models of advanced organic modules and printed circuit boards were used to explore these limits. Simulations of link performance performed with an internal link modeling tool allowed us to explore the effect of equalization and modulation formats at different data rates on link bit error rate and eye opening. Our link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signaling limits were then determined by extrapolating these hardware-correlated models to higher speeds, and these limits were compared to the results of recent work on on-board optical interconnects.

A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single “Holey” CMOS IC

We report here on the design, fabrication, and high-speed performance of a compact 48-channel optical transceiver module enabled by a key novel component: a “holey” Optochip. A single CMOS transceiver chip with 24 receiver (RX) and 24 laser diode driver circuits, measuring 5.2 mm × 5.8 mm, becomes a holey Optochip with the fabrication of forty-eight through-substrate optical vias (holes): one for each transmitter (TX) and RX channel. Twenty-four channel, 850-nm VCSEL and photodiode arrays are directly flip-chip soldered to the Optochip with their active devices centered on the optical vias such that optical I/O is accessed through the substrate of the CMOS IC. The holey Optochip approach offers numerous advantages: 1) full compatibility with top emitting/detecting 850-nm VCSELs/PDs that are currently produced in high volumes; 2) close integration of the VCSEL/PD devices with their drive electronics for optimized high-speed performance; 3) a small-footprint, chip-scale package that minimizes CMOS die cost while maximizing transceiver packing density; 4) direct coupling to standard 4 × 12 multimode fiber arrays through a 2-lens optical system; and 5) straightforward scaling to larger 2-D arrays of TX and RX channels. Complete transceiver modules, or holey Optomodules, have been produced by flip-chip soldering assembled Optochips to high-density, high-speed organic carriers. A pluggable connector soldered to the bottom of the Optomodule provides all module electrical I/O. The Optomodule footprint, dictated by the 1-mm connector pitch, is 21 mm × 21 mm. Fully functional holey Optomodules with 24 TX and 24 RX channels operate up to 12.5 Gb/s/ch achieving efficiencies (including both TX and RX) of 8.2 pJ/bit. The aggregate 300-Gb/s bi-directional data rate is the highest ever reported for single-chip transceiver modules.