Young Seog Kang

Applications of angular scatterometry for the measurement of multiply periodic features

Scatterometry is a novel optical metrology based on the analysis of light diffracted from a periodic sample. In the past the technology has been applied successfully to a variety of different grating types found in the manufacture of microelectronic devices. The scope of these applications, however, has been limited to structures that are singly periodic (periodicity = 1) in nature, i.e., gratings that are simple line and space structures with one periodic dimension. Rigorous coupled wave theory (RCWT), the underlying theory behind scatterometry measurements, can be applied to structures with a higher dimension of periodicity (periodicity > 1), although the computation is much more complex. In this paper we will discuss the application of scatterometry to structures with higher dimensions of periodicity, such as arrays of contact holes and DRAM cells. Details of the model, such as computation time and considerations for choosing a proper shape for the diffracting structures, will be presented. Sensitivity of the various parameters, such as the multiple critical dimensions and sidewall angles, will be discussed. Finally, results of measurements on contact hole and typical DRAM storage node patterns will be summarized. When compared to SEM, we will show correlation results that are greater than 0.9 for most applications, indicating that the technology can be applied successfully to such complicated structures. System matching between tools for these applications will also be discussed.

Process latitude extension in low k1 DRAM lithography using specific layer-oriented illumination design

Improvement of process latitude is tested in typical DRAM patterns by using the optimized illumination for each layer pattern. The optimized illumination for a specific layer is generated by modifying the Fourier transformed image of the layer and by using in-house illumination optimization program, which can simulate the maximum process latitude. These illumination shapes are compared with each other, and it is confirmed that both illuminations are similar in shape. The typical DRAM patterns are exposed using the optimized illuminations, and the process latitude is compared with typical annular illumination cases. It is certain that the process latitude using the optimized illumination is greater than the high sigma annular illumination. By using the optimized illumination, the enlarged process latitude makes it possible to use lower grade tools for a critical layer. It is expected that the lifetime of low-grade exposure tools can be extended by this illumination optimization technique.

Lens heating impact analysis and controls for critical device layers by computational method

We report that, based on our experimental data, lens heating (LH) impact on wafer image can be effectively controlled by using a computational method (cASCAL) on critical device layers with no request on tool time. As design rule shrinks down, LH control plays a key role in preventing the image deterioration caused by the LH-induced wavefront distortion during exposure. To improve LH prediction accuracy, 3-dimension structure of mask stack (M3D) is considered in calculating the electro-magnetic (EM) field that passes through the mask for full chip. Additionally, lens specific calibration (LSC) is performed on individual scanners to take the lens-to-lens variation into account. In data comparisons, we show that cASCAL performs very well as an ASCAL substitute, and that M3D and LSC improve the LH prediction accuracy of cASCAL.

Layer-specific illumination optimization by Monte Carlo method

Layer specific illumination has merits of enhancement of resolution, widening DOF and image fitness. For dense patterns like DRAM cell, layer specific illumination is a major candidate to drive low k1 lithography. To find out the best illumination for a specific pattern, diffracted image of the pattern and the ratio of captured first order to 0th order diffracted beam should be considered. By spectrum analysis, the best illumination is obtained for simple patterns like dense lines, brick wall, and dense contacts. In this paper, the procedure of obtaining the best illumination for specific patterns is presented. Comparing general illuminations such as annular, the resultant illumination is proved to have wider DOF and enhancement of resolution. The best illumination can also be found by Monte Carlo simulation. For simple one-dimensional case, its validity is proved. From the exposure results, wide DOF and enhancement of resolution is confirmed.

Improvement of inter-field CDU by using on-product focus control

This paper introduces to improve inter-field CDU with on-product focus control by diffraction based focus (DBF) method. For DBF target selection, a robust focus metrology for focus control was obtained, and the selected DBF target was integrated on each seven spot of a product reticle. For on-product focus control, previously on-product focus monitoring was performed, and the monitored lots showed a stable focus fingerprint. Based on the result, Z and Z/ Rx/Ry corrections per field on wafers were applied. Focus uniformity of controlled wafers was improved up to 29% in comparison with non-corrected ones. To demonstrate the improvement of inter-field CDU, Full CDs on wafers were measured by SEM. As a result, inter-field CDU for controlled wafers was improved by 16% (3σ) compared with noncontrolled wafers.

Analysis of overlay errors induced by exposure energy in negative tone development process for photolithography

Negative tone development (NTD) process with positive resist and organic solvent-based developer enhances image contrast and uses a light-field mask to make same feature in opposition to positive tone development (PTD). Due to extremely high transmission rate of a light-field mask, absorption of exposure energy on a mask becomes imperceptible. However, the exposure energy transmitted through the mask influences not only lens heating but also wafer heating. Overlay budget by wafer heating becomes a considerable amount in NTD process. In this paper, to clarify overlay change induced by wafer heating in NTD process, four different levels of exposure energy are applied and the overlay errors are deteriorated by increasing energy. Due to wafer heating, the remarkable correlation between Y-overlay errors and scanning direction are observed. Especially, Ty, RK8, and RK12 have mostly considerable correlation with scanning direction. In NTD process, to avoid this phenomenon, exposure energy has to be minimized. In case scanning direction dependency in overlay is not prevented by minimization of exposure energy, fingerprint correction in wafer field is able to reduce this overlay error.

Focus control budget analysis for critical layers of flash devices

As design rule shrinks down, on-product focus control became more important since available depth of focus (DOF) is getting narrower and also required critical dimension uniformity (CDU) becomes tighter. Thus monitoring, control the scanner focus error and reducing the focus control budget of scanner are essential for the production. There are some critical layers which has so narrow DOF margin that hardly be processed on old model scanners. Our study mainly focused on the analysis of the scanner focus control budget of such layers. Among the contributors to the focus budget, inter-field focus uniformity was turned out to be the most dominant. Leveling accuracy and intra-field focus uniformity were also dominant.

Overlay excursion monitoring using SEM image

More than decades the optical overlay metrology system is still using for the measurement. However, many results are reported on the subject of the mismatch between optical overlay measurement form overlay mark and real pattern registration that is caused by lens aberration, mask registration, dynamic distortion on chip level and wafer induced shift of overlay tool on wafer level. Therefore there are lots of report to investigate and resolve this gap. In this report, we study the measurement of overlay related value with slant measurement on real pattern. After etch a real pattern could be used for the overlay check at specific steps so that the registration excursion is checked using high resolution SEM image. Even though the slant value is not enough to obtain whole vector of overlay it is enough to check the overlay excursion along with critical direction. Also with specific structure the exact overlay can be measured and it is comparable with optical overlay value. Using this structure the Across Field Overlay Variation is successfully measured. The precision of the measurement is achieved same level of R and T on CD measurement. However there are still some limitations to be optimized on the algorithm because that is designed for the single contact-hole analysis to check the contact profile.

Process margin improvement through finger-print removal based on scanner leveling data

The next generation technology and emerging memory devices require gradually tighter lithographic focus control on imaging critical layers. Especially in case of BEOL process, big PDO (Process Dependent Offset) from large intra-field topography steps affects the process margin directly. There are couple of scanner options to reduce PDO, such as AGILE which provides several benefits. However, for certain use cases the AGILE sensor may not be the optimal solution. In this paper, we introduce the concept and development background of iFPC (intra-field Finger Print Correction). iFPC is a scanner option that removes the generic 3D fingerprint seen in the leveling data so that both process dependency and actual wafer topography are not followed during wafer exposure. In addition, we compare the degree of process margin improvement when applying iFPC compared to that of AGILE on a critical layer. The achieved results demonstrate that by applying iFPC it is possible to gain an additional 15~20nm DoF. In other words, on this use case our feasibility suggests that by removing the generic 3D fingerprint seen in the leveling data, it is possible to achieve a better focus performance than when trying to follow the topography during scanning. In conclusion, we found another good way to improve the process margin through this comparative experiment. Therefore, our next step will be to setup the methodology to select the use cases where iFPC is the optimal solution.

Scanner-to-scanner CD analysis and control in an HVM environment

Shrinking pattern sizes dictate that scanner-to-scanner variations for HVM products shrink proportionally. This paper shows the ability to identify (a subset of) root causes for mismatch between ArF immersion scanners using scanner metrology. The root cause identification was done in a Samsung HVM factory using a methodology (Proximity Matching Budget Breakdown or PromaBB) developed by ASML. The proper identification of root causes-1 helps to select what combination of scanner control parameters should be used to reduce proximity differences of critical patterns while minimizing undesirable side effects from cross-compensation. Using PromaBB, the difference between predicted and measured CD mismatch was below 0.2nm. PromaBB has been proposed for HVM implementation at Samsung in combination with other ASML fab applications: Pattern Matcher Full Chip (PMFC), Image Tuner and FlexWave.