Young-Shig Choi

Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop

The charge pump (CP) circuit is a key element in a phase-locked loop (PLL). Its function is to transform the Up and Down signals from the phase/frequency detector into current. In CMOS CPs, which have Up and Down switches made of p-channel MOS and n-channel MOS, respectively, a current mismatch occurs when dumping the charge to the loop filter. This current mismatch of the CP in the PLL generates fluctuations in the voltage-controlled-oscillator input and subsequently, a large phase noise on the PLL output signals. In this brief, a new CP with good current matching characteristics is proposed. By using a simple gain-boosting circuit, good current matching characteristics can be achieved with less than 0.1% difference of the Up/Down current over the CP output voltage ranges of 0.8-2.2 V and 0.5-1.2 V on 0.35-mum 3.3-V and 0.18-mum 1.8-V CMOS processes, respectively. The proposed CP circuit is simulated and verified by HSPICE with 0.35-mum 3.3-V and 0.18-mum 1.8-V CMOS parameters

An adaptive bandwidth phase locked loop with locking status indicator

This paper presents a new structure of phase locked loop (PLL) which changes its loop bandwidth according to the locking status. The proposed PLL consists of a conventional PLL and locking status indicator (LSI). The LSI decides the operating bandwidth of loop filter. When the PLL becomes out of lock, the PLL increases the loop bandwidth and achieves fast locking. When the PLL becomes in-lock, this PLL decreases the loop bandwidth and minimizes phase noise output. The PLL can achieve fast locking and low phase noise output at the same time. Proposed PLLs locking time is less than 100/spl mu/s and spur is -60dBc. It is simulated by HSPICE in a CMOS 0.35/spl mu/m process. Supply voltage and operating frequency are 3.3V and 1.28GHz, respectively.

A Negative Feedback Looped Voltage-Controlled Ring Oscillator With Frequency Voltage Converter

This paper proposes a negative feedback looped voltage-controlled ring oscillator (VCRO) with a frequency voltage converter (FVC) to suppress the phase noise. Measurement results of the negative feedback looped VCRO fabricated in a one-poly six-metal 1.8-V 0.18- μm CMOS process show that the phase noises are -90, -90, -94, -102, and -110 dBc/Hz at 1-kHz, 10-kHz 100-kHz, 1-MHz, and 10-MHz offset from 922.9-MHz output frequency, respectively. The proposed negative feedback looped VCRO reduces the phase noise of a conventional VCRO by 35 ~ 8 dB from 1 kHz to 1 MHz. Measurement results show that the FVC can be combined with various VCRO and LC voltage-controlled oscillator architectures in a negative feedback loop to improve their phase-noise characteristic further.

A low jitter phase-lock loop based on a new adaptive bandwidth controller

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO at approximately -80dBc

A Low-Jitter DLL-Based Clock Generator with Two Negative Feedback Loops

Abstract—This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal 0.18 µm CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz. Index Terms—clock generator, delay locked loop, delay-time variance voltage converter I. I NTRODUCTION As the speed performance of recent chips rapidly increases, more emphasis is placed on suppressing jitter in high frequency clock signal. Phase locked loops (PLL’s) and delay locked loops (DLL’s) have been widely used in microprocessors and memory chips to generate on-chip clock signals. While the phase noise of PLL’s is accumulated, that of DLL’s is not accumulated, and thus, the clock signal generated from DLL’s has lower jitter. For the clock multiplication, DLL requires evenly spaced edges from delay stages in voltage controlled delay line (VCDL). They span one period of reference signal. These evenly spaced edges are combined to form a pattern of higher frequency transition and eventually generate the desired high frequency clock signal. Timing uncertainty of edges due to PVT variations among the delay stages in VCDL causes a larger jitter. An edge combiner is used to generate a higher frequency signal [1]. To suppress the timing uncertainty, novel techniques have been published. The self-calibrated technique by using shift averaging VCDL reduces the timing uncertainty of delay stages in VCDL but it has a difficulty of suppressing the timing uncertainty accurately [2]. The phase averaging and interpolation by using resistor arrays has been proposed to suppress the delay mismatch of delay stages but it requires a large area for resistor arrays [3]. The closet edge selection method digital DLL has been proposed to suppress the timing uncertainty [4]. The delay mismatches among delay stages are compared by using multiple phase detectors to suppress delay mismatch [5]. The multiple phase detectors which are sensitive to process variations may generate variation among their output. The self-calibration method that consists of a delay calibration buffer and a timing error comparator is used to reduce the delay mismatch [6]. The current mismatch of the timing error comparator can cause the systematic timing uncertainty. In this letter, additional negative feedback loops for each delay cells in VCDL are introduced to suppress timing uncertainty (delay mismatches) of every delay stage. It has been implemented in 0.18µm CMOS process and shown the low measured jitter of the proposed DLL.

A ΣΔ Fractional-N PLL with Multiple Charge Pumps and Capacitance Scaling Scheme

A novel SigmaDelta fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status for fast locking and fractional spur suppressing while keeping LF capacitors small enough to be integrated into a single PLL chip. It has been simulated by HSPICE in a CMOS 0.35mum process, and shows that locking time is less than 8mus with the small size of LF capacitors, 200pF and 17pF, and 2.8KOmega resistor

A 2.4-GHz latch-structured power amplifier for Bluetooth

A two-stage class E power amplifier operating at 2.4GHz was designed in a 0.25-/spl mu/m CMOS process for class-1 Bluetooth applications. The power amplifier employs a class-E topology in order to obtain high efficiency by exploiting its soft-switching property. The latch-structured design of the preamplifier with auxiliary amplifiers enables its output signal to be as sharp as possible for the soft switching of the next stage power amplifier. This improves the overall efficiency of the proposed power amplifier which has a PAE of 65.8%,a power gain of 20dB and an output power of 20dBm.

Fabrication and characteristics of the suppressed sidewall injection magnetotransistor using a CMOS process

We report the implementation of a novel suppressed sidewall injection magnetotransistor. The novel device overcomes the restriction of the standard CMOS technology and achieves high linearity. The fabricated device is designed, based on the Hynix 0.6 /spl mu/m standard CMOS technology and is experimentally verified. Experimental results show that the change of the collector current is extremely linear as a function of the magnetic induction at I/sub B/=500 /spl mu/A, V/sub CE/=2 V and V/sub SE/=5 V. The relative sensitivity is up to 120%/T. The nonlinearity of the fabricated device is measured about 1.4%.

A fast locking DLL clock synthesizer

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. The DLL has several inherent advantages, such as no jitter accumulation, fast locking and easy integration of the loop filter. This paper proposes a new programmable DKK that includes a new PFD (phase frequency detector) and a new VCDL (voltage controlled delay line) to generate multiple clicks. It can generate clocks from 3 to 10 times of input clock with 5/spl mu/s locking time. The HSPICE simulation with 0.35/spl mu/m CMOS process verifies the proposed DLL operating in the frequency range of 300 MHz to 1 GHz.

Characteristics of the Suppressed Sidewall Injection Magnetotransistor using a CMOS Process

We report the implementation of a novel suppressed sidewall injection magnetotransistor. The novel device overcomes the restriction of the standard CMOS technology and achieves high linearity. The fabricated device is designed, based on the Hynix 0.6 /spl mu/m standard CMOS technology and is experimentally verified. Experimental results show that the change of the collector current is extremely linear as a function of the magnetic induction at I/sub B/=500 /spl mu/A, V/sub CE/=2 V and V/sub SE/=5 V. The relative sensitivity is up to 120%/T. The nonlinearity of the fabricated device is measured about 1.4%.