Young-Taek Lee

A 3.3 V 1 Gb multi-level NAND flash memory with non-uniform threshold voltage distribution

A 1 Gb NAND flash memory with 2b per cell uses 0.15 /spl mu/m CMOS and achieves simultaneous operation of 4 independent banks with 1.6 GMB/s program throughput. Fusing enables changing to 512 Mb 1b-per-cell NAND flash memory. Wordline ramping minimizes noise and peak current. Disturb mechanisms and noise related V/sub TH/ distribution shifts are minimized to improve read margins.

A 3.3 V 4 Gb four-level NAND flash memory with 90 nm CMOS technology

A 4 Gb NAND flash memory with 2 b/cell uses 90 nm CMOS to achieve simultaneous data load during program operation with 1.6 MB/s program throughput. Fuse or pad-bonding switches it to a 2 Gb 1 b/cell NAND flash memory. The row decoder located in the middle of the cell array reduces W/L rise time and coupling noise. A program-after-erase technique and lowered floating poly thickness minimize cell Vth distribution.

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with original data seamlessly without a timing bubble. A 288 Mb SDRAM has been designed using the proposed scheme combined with fast cycling core techniques to have both high I/O bandwidth and fast random cycling. Measured results show that the chip exhibits per-pin data rate of 8 Gb/s and row cycle time of 9.6 ns