Younggun Han

Low temperature deposition of ITO thin films by ion beam sputtering

Abstract An ion beam sputtering system was used for the deposition of indium-tin-oxide (ITO) films at low temperatures (below 200°C). The electrical and optical properties and the microstructure were highly dependent on the growth temperature, the oxygen partial pressure and the ion beam energy. A reasonable resistivity (3.5×10 −4 Ωcm) was measured in the films deposited by Ar ion sputtering at as low as 50°C. In the films by Ar ion sputtering, the lowest resistivity was 1.5×10 −4 Ωcm at 100°C. Oxygen addition to the sputtering gas increased the resistivity, especially at low substrate temperatures. The addition of oxygen to the sputtering gas changed the microstructure from ‘domain’ (sub-grain) structure at 100°C to ‘grain’ structure. The oxygen addition induced the change in O/In ratios. The film composition also depended on the ion beam energy. The optical transmittance higher than 80% in the visible range was measured in the films deposited at above 100°C. The optical band gap calculated from the transmittance spectra was approximately 4.2 eV.

Effects of substrate treatment on the initial growth mode of indium-tin-oxide films

The initial growth mode of indium tin oxide (ITO) on polycarbonate (PC) substrates was investigated. Some of the PC substrates were bombarded by 1-keV Ar ions in an oxygen environment to modify the substrate surface before ITO sputter deposition. The initial part of the film growth was transformed from a three-dimensional island growth to a two-dimensional like growth as a result of the surface treatment. The change of the growth mode was attributed to oxygen-bound functional groups newly formed on the PC surface. Models based on thermodynamic theory and on atomic kinetic approach are presented to explain the transition, respectively.

Influence of ITO surface modification on the growth of CdS and on the performance of CdS/CdTe solar cells

We treated the surface of indium-tin oxide (ITO) substrates in two ways, (i) coating of thin insulating ITO layer or (ii) irradiation of the surface with accelerated ions, and investigated the change in sheet resistance (R s h ) and the water-contact angle (WCA). R s h increased with the thickness of the insulating ITO layer or with the ion dose. WCA dropped as a result of the surface treatment to <15°. The microstructure, the surface morphology, the optical transmittance, and the stoichiometry of CdS improved with the surface treatment. CdS/CdTe solar cells showed a better performance as a result of ITO surface treatment.

Influence of seed layers on microstructure and electrical properties of indium-tin oxide films

Films of indium-tin oxide (ITO) were deposited by ion-beam sputtering. Two types of seed layers of ITO were deposited prior to bulk-layer deposition. The types of seed layers were determined by ion species, namely, either pure Ar+ or a mixture of Ar+ and O2+. The microstructure and the preferred orientation of the bulk films mimicked those of the seed layer. Films with larger grains were obtained when the seed layer was used. The electron mobility did not depend on the type of microstructure. The ability to control the microstructure without sacrificing the electrical conductivity was demonstrated.

Influence of uniaxial mechanical stress on the high frequency performance of metal-oxide-semiconductor field effect transistors on (100) Si wafer

The effects of uniaxial mechanical stress on the radio frequency performance of n- and p-metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated up to 10 GHz. Under tensile stress, the gate transconductance (gm) increases in the n-MOSFETs while it decreases in the p-MOSFETs, whereas the results were vice versa for compressive stress. The total gate capacitance (CG) extracted from scattering parameters increases (decreases) under tensile (compressive) stress for both n- and p-MOSFETs, which is explained by the variation in the effective mass perpendicular to the Si/SiO2 interface. The cut-off frequency (fT) varies in inverse proportion to the CG variation.

Evaluation of residual stress caused by flip-chip bonding process using piezo-resistor embedded test element group chips

The stress of ICs caused by flip-chip bonding process is evaluated using piezo-resistor embedded test element group (TEG) chips. The TEG size is 9 × 9 mm2 with 550 μm in thickness. After non-conductive film (NCF) coating, the TEG chip is connected to the substrate by flip-chip bonding. The stress inside the chip was obtained in each process of flip-chip bonding by measuring the change in piezo-resistance. After bonding, the compressive stress is high in the center of TEG chips and the stress was lower towards the corner. The stress at elevated temperatures up to 123 °C is also measured. The compressive stress decreases with increasing temperature. The comparison between NCF and under-fill (UF) materials is performed through the same process.

Process Feasibility and Reliability Performance of Fine Pitch Si Bare Chip Embedded in Through Cavity of Substrate Core

We demonstrate the concept and fabrication of through cavity core device-embedded substrate for fine-pitch Si bare chips with pad pitches down to 60 μm. Instead of using a real active Si chip, we embedded a Si test element group inside a through cavity of the core. To adjust to the thickness of the passive device with a maximum thickness of 150 μm, the Si chip was thinned to 120 μm, not including bump height. After placing a chip, the cavity is filled by laminating a two-layer structure Ajinomoto build-up film from both sides of the substrate core. To accurately place the chip in the cavity, we strictly controlled the lamination conditions and curing temperature of the epoxy resin. Laser via drilling produced the best alignment for fine-pitch small pads using the local alignment marks of each test frame kit with overhead epoxy resin of the Cu mark pattern removed. To produce a high-quality microvia interconnection to the Al pad of the Si chip, we used a new, combined desmearing technique that included a plasma treatment with CF4 + O2 mixed gas. Finally, we discussed the production yield and reliability of the fine-pitch Si bare chip-embedded substrate using the daisy-chain structure consisted of Si chip pattern, microvia on Si pad, and substrate tracks.

Residual stress evaluation of flip-chip bonding with non-conductive films on organic substrate and silicon interposer by piezo-sensor embedded test element group chips

The stress of integrated circuits caused by flip-chip bonding (FCB) is evaluated using piezo-sensor embedded test element group (TEG) chips. After non-conductive film (NCF) coating, the TEG chips are connected to the organic substrate and silicon interposer by FCB. The chip size is 9×9 mm2 with 200μm in thickness. The stress inside the chip is obtained in each process of FCB by measuring the change in piezo-resistance. On the organic substrate, the compressive stress after bonding is high in the center of TEG chips and the stress becomes lower towards the corner. On the silicon interposer, the compressive stress is low compared to the organic substrate. The stress at elevated temperatures up to 120 °C is also measured. On the organic substrate, the compressive stress decreases with increasing temperature. For silicon interposer case, on the other hand, the stress is almost constant with temperature.

Enhanced CdTe solar cell performance through surface engineering

Surface of indium-tin oxide (ITO) substrate were irradiated with accelerated Ar/sup +/, N/sub 2//sup +/, O/sub 2//sup +/ and H/sub 2//sup +/ ions (1 keV) at different doses. The change in sheet resistance (R/sub sh/), the water-contact angle (WCA) and the composition of ITO were measured. R/sub sh/ slightly increased with the ion dose. WCA dropped to less than 15/spl deg/ and the composition shifted to oxygen-rich. CdS films grown on ITO by chemical bath deposition showed an improvement in terms of the microstructure, the surface morphology, the optical transmittance, and the stoichiometry. X-ray photoluminescence was performed on CdS/ITO glass for the first time. The performance of CdTe/CdS solar cells was improved as a result of ITO surface treatments, this being due to improvements in the physical structure of the CdS interfaces.

Evaluation of relationship between residual stress of ICs and package warpage caused by flip-chip bonding

Relationship between the stress of ICs and package warpage caused by flip-chip bonding is evaluated using piezoresistor chip and is measured by Moiré measurement method. The die size is 9×9 mm2 with 200μm and 550μm in thickness. After non-conductive film laminating, the TEG chip is connected to the organic substrate or the Si interposer by FC bonding. The stress inside the chip was obtained in process of FC bonding by measuring the change in piezo-resistance. The warpage measured by moiré analysis method is in good agreement with the measured residual stress.