Youngkwon Jo

Electrical models of TFT‐LCD panels for circuit simulations

— As thin-film-transistor liquid-crystal-display (TFT-LCD) panels become larger and provide higher resolution, the propagation delay of the row and column lines, the voltage modulation of Vcom, and the response time of the liquid crystal affect the display images now more than in the past. It is more important to understand the electrical characteristics of TFT-LCD panels these days. There are several commercial products that simulate the electrical and optical performance of TFT-LCDs. Most of the simulators are made for panel designers. However, this research is for circuit, system, and panel designers. It is made in a SPICE and Cadence environment as a commercial circuit-design tool. For circuit and system designers, it will help to design the circuit around a new driving method. Also, it can be easily modified for every situation. It also gives panel designers design concepts. This paper describes the electrical model of a 15-in. XGA (1024 × 768) TFT-LCD panel. The parasitic resistance and capacitance of the panel are obtained by 3-D simulation of a subpixel. The accuracy of these data is verified by the measured values of an actual panel. The developed panel simulation platform, the equivalent circuit of a 1 5-in. XGA panel, is simulated by HSPICE. The results of simulation are compared with those of experiment, according to changing the width of the OE signal. The proposed simulation platform for modeling TFT-LCD panels can be especially applied to large-sized LCD TVs. It can help panel and circuit designers to verify their ideas without making actual panels and circuits.

A mixed-structure delay locked-loop with wide range and fast locking

This paper describes an all digital locked-loop (DLL) with a mixed structure of measure-controlled DLL (MCDLL) and register-controlled DLL (RCDLL). The DLL utilized time to digital converter (TDC) and digital to time converter (DTC) using ring counter for wide range operation with small area, fast lock and duty cycle correction (DCC). Simulation results show lock time less than 40 cycles, 1% duty correction error from 50plusmn10% duty external clock, 12mW power dissipation at 800MHz with a 1.5V supply voltage and a wide locking range from 100MHz to 800MHz in a 0.18mum CMOS technology

A register controlled delay locked loop using a TDC and a new fine delay line scheme

This paper presents a register controlled delay lock loop (RCDLL) with a time-to-digital converter (TDC) and a new fine delay line (FDL) scheme. The architecture of the proposed DLL uses a time-to-digital converter (TDC), a digital-to-time converter (DTC) scheme for short length of coarse delay line (CDL), and a open loop duty cycle corrector (DCC). While the conventional DLL has two feedback loops, the DLL with an open loop DCC has only one loop. So, it occupies a small area compared to the conventional one. Moreover, new FDL scheme is proposed which is capable of seamless boundary switching with a fixed delay step. HSPICE simulation results are based with ANAM 0.18mum 1P6M CMOS process with 1.5V power supply voltage. Upon the simulation results, the proposed DLL operates correctly from 200MHz to 800MHz. The power consumption is less than 24mW at 800MHz. The active area of the design is 0.178mm2

An Intra-panel Interface for Large Size FPDs with High Resolution And Definition

This paper describes an intra-panel interface which can be applied to a large panel with high resolution and high definition. For good signal integrity and low electro-magnetic interference level, four level signaling is used. And to reduce PCB size, point to point signaling is used. The interface supports WUXGA, 12 bit color depth panel which has larger than 30 inch size. It is designed with a 0.18 um CMOS process. And measurements show it works properly in 25 cm long PCB, which is the same condition of 30 inch panel size.

An intra-panel interface using three transmission lines for flat panel displays

In this paper, a new signaling scheme is proposed for intra-panel interface using three transmission lines for flat panel displays. The interface utilizes multi-level current signaling with delta-y configured resistor network. It increases the number of symbols and differentiates the symbols with pseudo differential signaling. The interface utilizes input buffer with low input impedance to reduce driving current. Therefore, the interface has lower frequency with low driving current when it has same data rate as conventional intra-panel interface. As a result, electromagnetic interference can be lowered. The interface is fabricated using a 0.18um CMOS technology, and its measured bit error rate was 3.9 × 10-11.