Yu Jinshan

A fast transient response low dropout regulator with current control methodology

A transient performance optimized CCL-LDO regulator is proposed. In the CCL-LDO, the control method of the charge pump phase-locked loop is adopted. A current control loop has the feedback signal and reference current to be compared, and then a loop filter generates the gate voltage of the power MOSFET by integrating the error current. The CCL-LDO has the optimized damping coefficient and natural resonant frequency, while its output voltage can be sub-1-V and is not restricted by the reference voltage. With a 1 μF decoupling capacitor, the experimental results based on a 0.13 μm CMOS process show that the output voltage is 1.0 V; when the workload changes from 100 μA to 100 mA transiently, the stable dropout is 4.25 mV, the settling time is 8.2 μs and the undershoot is 5.11 mV; when the workload changes from 100 mA to 100 μA transiently, the stable dropout is 4.25 mV, the settling time is 23.3 μs and the overshoot is 6.21 mV. The PSRR value is more than −95 dB. Most of the attributes of the CCL-LDO are improved rapidly with a FOM value of 0.0097.

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology

A 2-Gsample/s 8-b analog-to-digital converter in 0.35 μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS. Digital calibration technology is used for the offset and gain corrections of the S/H circuit, the offset correction of preamplifier, and the gain and clock phase corrections between channels. As a result of testing, the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

A direct digital frequency synthesizer with high-speed current-steering DAC

A high-speed SiGe BiCMOS direct digital frequency synthesizer (DDS) is presented. The design integrates a high-speed digital DDS core, a high-speed differential current-steering mode 10-bit D/A converter, a serial/parallel interface, and clock control logic. The DDS design is processed in 0.35 μm SiGe BiCMOS standard process technology and worked at 1 GHz system frequency. The measured results show that the DDS is capable of generating a frequency-agile analog output sine wave up to 400+ MHz.

A new approach to development of composite Web Services

With the requirement for complex Web Services steadily increasing, there is a growing interest for reusing basic, existing Web Services to composite new ones. We present a composite Web Services development approach driven by model driven architecture (MDA): using UML (Unified Modeling Language) class diagram to model structure PIM (Plateform Independent Platform) and UML activity diagram to model behavior PIM, then by model transformation converting the PIMs to specific Web Services specification plat-forms and execution platform to get the corresponding PSMs (platform specific models). The main contributions of this paper are the all-around solution to Web Services composition development and the transformation rules for structure and behavior model of Web Services between PIMs and PSMs.