Yuan Taur

Device scaling limits of Si MOSFETs and their application dependencies

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's

Quantum-mechanical modeling of electron tunneling current from the quantized inversion layer of ultra-thin-oxide (<40 /spl Aring/) nMOSFETs is presented, together with experimental verification. An accurate determination of the physical oxide thickness is achieved by fitting experimentally measured capacitance-versus-voltage curves to quantum-mechanically simulated capacitance-versus-voltage results. The lifetimes of quasibound states and the direct tunneling current are calculated using a transverse-resonant method. These results are used to project an oxide scaling limit of 20 /spl Aring/ before the chip standby power becomes excessive due to tunneling currents,.

CMOS scaling into the nanometer regime

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFETs, low-temperature CMOS, and double-gate MOSFETs, which may lead to the outermost limits of silicon scaling.

An analytical solution to a double-gate MOSFET with undoped body

A one-dimensional (1-D) analytical solution is derived for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poissons equation. The solution gives closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage. A threshold criterion is derived which serves to quantify the gate work function requirements for a double-gate CMOS.

Generalized scale length for two-dimensional effects in MOSFETs

We derive a new scale length for two-dimensional (2-D) effects in MOSFETs and discuss its significance. This derivation properly takes into account the difference in permittivity between the Si channel and the gate insulator, and thus permits an accurate understanding of the effects of using insufficiently scaled oxide or thicker higher permittivity gate insulators. The theory shows that the utility of higher dielectric constant insulators decreases for /spl epsiv///spl epsiv//sub 0/>-20, and that in no event should the insulator be thicker than the Si depletion depth. The approach is also applied to double-gated FET structures, resulting in a new more general scale length formula for them, too.

25 nm CMOS design considerations

This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supply voltage, is presented. A highly 2D nonuniform profile (super-halo) is shown to yield low off-currents while delivering a significant performance advantage for a 1.0 V power supply. Several key issues, including source-drain doping requirements, band-to-band tunneling, and poly depletion effects, are examined and quantified. It is projected, based on Monte-Carlo simulations, that the delay performance of 25 nm CMOS is 3/spl times/ higher than 100 nm CMOS, and that the nFET f/sub T/ exceeds 250 GHz.

A new 'shift and ratio' method for MOSFET channel-length extraction

A shift-and-ratio method for extracting MOSFET channel length is presented. In this method, channel mobility can be any function of gate voltage, and high source-drain resistance does not affect extraction results. It is shown to yield more accurate and consistent channel lengths for deep-submicrometer CMOS devices at room and low temperatures. It is also found that, for both nFET and pFET, the source-drain resistance is essentially independent of temperature from 300 to 77 K.<<ETX>>

A 2-D analytical solution for SCEs in DG MOSFETs

A two-dimensional (2-D) analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the subthreshold region by solving Poissons equation in a 2-D boundary value problem. It is shown that the subthreshold current, short-channel threshold voltage rolloff and subthreshold slope predicted by the analytical solution are in close agreement with 2-D numerical simulation results for both symmetric and asymmetric DG MOSFETs without the need of any fitting parameters. The analytical model not only provides useful physics insight into short-channel effects, but also serves as basis for compact modeling of DG MOSFETs.

Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides

The electrical characteristics (C-V and I-V) of n+ - and p+ -polysilicon-gated ultrathinoxide capacitors and FETs were studied extensively to determine oxide thickness and to evaluate tunneling current. A quantum-mechanical model was developed to help understand finite inversion layer width, threshold voltage shift, and polysilicon gate depletion effects. It allows a consistent determination of the physical oxide thickness based on an excellent agreement between the measured and modeled C-V curves. With a chip standby power of ≤0.1 W per chip, direct tunneling current can be tolerated down to an oxide thickness of 15-20 A. However, transconductance reduction due to polysilicon depletion and finite inversion layer width effects becomes more severe for thinner oxides. The quantum-mechanical model predicts higher threshold voltage than the classical model, and the difference increases with the electric field strength at the silicon/oxide interface.

An analytic potential model for symmetric and asymmetric DG MOSFETs

This paper presents an analytic potential model for long-channel symmetric and asymmetric double-gate (DG) MOSFETs. The model is derived rigorously from the exact solution to Poissons and current continuity equation without the charge-sheet approximation. By preserving the proper physics, volume inversion in the subthreshold region is well accounted for in the model. The resulting analytic expressions of the drain-current, terminal charges, and capacitances for long-channel DG MOSFETs are continuous in all operation regions, i.e., linear, saturation, and subthreshold, making it suitable for compact modeling. As no fitting parameters are invoked throughout the derivation, the model is physical and predictive. All parameter formulas are validated by two-dimensional numerical simulations with excellent agreement. The model has been implemented in Simulation Program with Integrated Circuit Emphasis version 3 (SPICE3), and the feasibility is demonstrated by the transient analysis of sample CMOS circuits.