Yuanfeng Wen

CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM

Increasingly, cyber attacks (e.g., kernel rootkits) target the inner rings of a computer system, and they have seriously undermined the integrity of the entire computer systems. To eliminate these threats, it is imperative to develop innovative solutions running below the attack surface. This paper presents MGuard, a new most inner ring solution for inspecting the system integrity that is directly integrated with the DRAM DIMM devices. More specifically, we design a programmable guard that is integrated with the advanced memory buffer of FB-DIMM to continuously monitor all the memory traffic and detect the system integrity violations. Unlike the existing approaches that are either snapshot-based or lack compatibility and flexibility, MGuard continuously monitors the integrity of all the outer rings including both OS kernel and hypervisor of interest, with a greater extendibility enabled by a programmable interface. It offers a hardware drop-in solution transparent to the host CPU and memory controller. Moreover, MGuard is isolated from the host software and hardware, leading to strong security for remote attackers. Our simulation-based experimental results show that MGuard introduces no speed overhead, and is able to detect nearly all the OS-kernel and hypervisor control data related rootkits we tested.

Back to the Future: Using Magnetic Tapes in Cloud Based Storage Infrastructures

Data backup and archiving is an important aspect of business processes to avoid loss due to system failures and natural calamities. As the amount of data and applications grow in number, concerns regarding cost efficient data preservation force organizations to scout for inexpensive storage options. Addressing these concerns, we present Tape Cloud, a novel, highly cost effective, unified storage solution. We leverage the notably economic nature of Magnetic Tapes and design a cloud storage infrastructure-as-a-service that provides a centralized storage platform for unstructured data generated by many diverse applications. We propose and evaluate a proficient middleware that manages data and IO requests, overcomes latencies and improves the overall response time of the storage system. We analyze traces obtained by live archiving applications to obtain workload characteristics. Based on this analysis, we synthesize archiving workloads and design suitable algorithms to evaluate the performance of the middleware and storage tiers. From the results, we see that the use of the middleware provides close to 100% improvement in task distribution efficiency within the system leading to a 70% reduction in overall response time of data retrieval from storage. Due to its easy adaptability with the state of the art storage practices, the middleware contributes in providing the much needed boost in reducing storage costs for data archiving in cloud and colocated infrastructures.

Multi-processor architectural support for protecting virtual machine privacy in untrusted cloud environment

Virtualization is fundamental to cloud computing because it allows multiple operating systems to run simultaneously on a physical machine. However, it also brings a range of security/privacy problems. One particularly challenging and important problem is: how can we protect the Virtual Machines (VMs) from being attacked by Virtual Machine Monitors (VMMs) and/or by the cloud vendors when they are not trusted? In this paper, we propose an architectural solution to the above problem in multi-processor cloud environments. Our key idea is to exploit hardware mechanisms to enforce access control over the shared resources (e.g., memory spaces), while protecting VM memory integrity as well as inter-processor communications and data sharing. We evaluate the solution using full-system emulation and cycle-based architecture models. Experiments based on 20 benchmark applications show that the performance overhead is 1.5%--10% when access control is enforced, and 9%--19% when VM memory is encrypted.

Energy efficient hybrid display and predictive models for embedded and mobile systems

Electrophoretic displays (EPDs) and organic light emitting diode (OLEDs) are two key technologies used in mobile de-vices. In this paper, we propose the design of an integrated hybrid display combining a transparent OLED (TOLED) and a low power EPD, which is adaptive to show contents of a frame partially on either the TOLED or the EPD. A windows-based predictive model and a calibration algorithm on TOLED are introduced to decide how frame contents can be split between the two displays for achieving the best tradeoff between power reduction and user experiences. A simulation environment that can estimate both the energy consumption and optical properties of the proposed hybrid display is set up based on actual physical measurements. Simulation results show that the predictive model can make right decisions on choosing proper displays in over 90% of the test cases, and this new display design can save over 70% power under many mobile application contexts and still sup-port contents that require fast update rates.

Worst case response time for real-time software transactional memory

Software transactional memory (STM) is used to control access to shared resources. The worst case response time (WCRT) estimation is different from the classical preemptive or nonpreemptive model due to its abort-restart nature. In this paper, we derive a WCRT for a STM system using lazy conflict detection. A WCRT example is also given.

Time petri nets for schedulability analysis of the transactional event handlers of P-FRP

Priority-based FRP (P-FRP) is a functional programming formalism for reactive systems that guarantees real-time response. Preempted tasks in P-FRP are aborted and have to restart when no higher priority tasks are present in the execution queue. The abort and eventual restart makes the response time of a lower priority task completely dependent on the execution pattern of higher priority tasks. Exact schedulability analysis methods of P-FRP that have been presented so far require the evaluation of all release scenarios of higher priority tasks. Unfortunately, the number of such scenarios scales exponentially with the size of the task set, making exact schedulability analysis of this execution model a computationally expensive proposition. The formal method of Time Petri Net (TPN) has previously been used for schedulability analysis of preemptive and non-preemptive models. TPNs for P-FRP or other transaction like execution models have not been developed yet. In this paper, we develop TPN models for the transactional execution model of P-FRP and show that TPNs offer an efficient alternative for schedulability analysis of this model. We have implemented our TPNs in the model checker ROMEO and have validated the correctness of our models through experimental task sets.

Fault resilient physical neural networks on a single chip

Device scaling engineering is facing major challenges in producing reliable transistors for future electronic technologies. With shrinking device sizes, the total circuit sensitivity to both permanent and transient faults has increased significantly. Research for fault tolerant processors has primarily focused on the conventional processor architectures. Neural network computing has been employed to solve a wide range of problems. This paper presents a design and implementation of a physical neural network that is resilient to permanent hardware faults. To achieve scalability, it uses tiled neuron clusters where neuron outputs are efficiently forwarded to the target neurons using source based spanning tree routing. To achieve fault resilience in the face of increasing number of permanent hardware failures, the design proactively preserves neural network computing performance by selectively replicating performance critical neurons. Furthermore, the paper presents a spanning tree recovery solution that mitigates disruption to distribution of neuron outputs caused by failed neuron clusters. The proposed neuron cluster design is implemented in Verilog. We studied the fault resilience performance of the described design using a RBM neural network trained for classifying handwritten digit images. Results demonstrate that our approach can achieve improved fault resilience performance by replicating only 5% most important neurons.

Tape Cloud: Scalable and Cost Efficient Big Data Infrastructure for Cloud Computing

Magnetic tapes have been a primary medium of backup storage for a long time in many organizations. In this paper, the possibility of establishing an inter-network accessible, centralized, tape based data backup facility is evaluated. Our motive is to develop a cloud storage service that organizations can use for long term storage of big data which is typically Write-Once-Read-Many. This Infrastructure-as-a-Service (IaaS) cloud can provide the much needed cost effectiveness in storing huge amounts of data exempting client organizations from high infrastructure investments. We make an attempt to understand some of the limitations induced by the usage of tapes by studying the latency of tape libraries in scenarios most likely faced in the backing up process in comparison to its hard disk counterpart. The result of this study is an outline of methods to overcome these limitations by adopting novel tape storage architectures, filesystem, schedulers to manage data transaction requests from various clients and develop faster ways to retrieve requested data to extend the applications beyond backup. We use commercially available tapes and a tape library to perform latency tests and understand the basic operations of tape. With the optimistic backing of statistics that suggests the extensive usage of tapes to this day and in future, we propose an architecture to provide data backup to a large and diverse client base.

Utilisation bounds of P-FRP tasks

Priority-based functional reactive programming (P-FRP) is a new functional programming formalism for developing safety-critical embedded systems. P-FRP allows static priority assignment and guarantees real-time response by preempting lower priority tasks. Due to the state-less nature of functional programmes, preempted tasks in P-FRP are aborted and have to restart after the higher priority tasks have completed execution. Since the execution semantics of P-FRP are different from the classical preemptive model of execution, existing utilisation-based sufficient conditions cannot be applied. In this paper, we derive a new utilisation-based sufficient schedulability condition for P-FRP, and validate it using experimental task sets. We then compare the sufficient schedulability condition of P-FRP with that of the preemptive model to demonstrate the severe restrictions on task set sizes in P-FRP. Effect on the utilisation bound under conditional preemption has also been analysed.

Towards optimal priority assignments for the transactional event handlers of P-FRP

Priority-based Functional Reactive Programming (P-FRP) is a new functional programming formalism for real-time systems. P-FRP allows static priority assignment and guarantees real-time response by preempting lower priority tasks. Due to the state-less nature, preempted tasks are aborted and restarted after higher priority tasks have completed execution. Therefore, the rate-monotonic (RM) priority assignment is not optimal in P-FRP, and it has been unknown whether an optimal fixed priority assignment can even exist for such an execution model. In this paper, we first present the priority assignment characteristics of P-FRP. We then discuss the priority assignment in a task set with two tasks. We derive the conditions when the RM priority assignment is optimal and show that at least one of RM or utilization-monotonic (UM) is the optimal for the task set with two tasks. We prove the optimal priority assignment for a general P-FRP system having more than two tasks exists when the period of the task is a multiple of others. Experimental results using task sets of different sizes are also presented.