Yuangang Wang

An energy efficient and low cross-talk CMOS sub-THz I/O with surface-wave modulator and interconnect

Free-space EM-wave based GHz interconnect has significant loss and crosstalk that cannot be deployed as low-power and dense I/Os for future network-on-chip (NoC) integration of many-core and memory. This paper proposes an energy-efficient and low-crosstalk sub-THz (0.1T-1T) I/O with use of surface-wave based modulator and interconnects in CMOS. By introducing sub-wavelength periodical corrugation structure onto transmission line, the surface-wave is established to propagate signal that is strongly localized on surface of top-layer metal wire, which results in low coupling into lossy substrate and neighboring metal wires. As such, significant power saving and cross-talk reduction can be observed with high communication bandwidth. In addition, a high on/off-ratio surface-wave modulator is also proposed to support on-chip THz communication. As designed in 65nm CMOS, the results have shown that the proposed surface-wave I/O interface achieves 25Gbps data rate and 0.016pJ/bit/mm energy efficiency at 140GHz carrier frequency over 20mm surface-wave channels. They can be placed with 2.4μm channel spacing and a -20dB crosstalk ratio. The surface-wave modulator also achieves significant reduction of radiation loss with 23dB extinction ratio.

An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar

Convolutional neural network (CNN) based machine learning requires a highly parallel as well as low power consumption (including leakage power) hardware accelerator. In this paper, we will present a digital ReRAM crossbar based CNN accelerator that can achieve significantly higher throughput and lower power consumption than state-of-arts. The CNN is trained with binary constraints on both weights and activations such that all operations become bitwise. With further use of 1-bit comparator, the bitwise CNN model can be naturally realized on a digital ReRAM-crossbar device. A novel sneak-path-free ReRAM-crossbar is further utilized for large-scale realization. Simulation experiments show that the bitwise CNN accelerator on the digital ReRAM crossbar achieves 98.3% and 91.4% accuracy on MNIST and CIFAR-10 benchmarks, respectively. Moreover, it has a peak throughput of 792GOPS at the power consumption of 6.3mW, which is 18.86 times higher throughput and 44.1 times lower power than CMOS CNN (non-binary) accelerators.

A 60GHz digitally-assisted power amplifier with 17.2dBm P sat , 11.3% PAE in 65nm CMOS

A digitally-assisted CMOS 60GHz PA is reported with high output power and improved power efficiency during power back-off. To combine large number of CMOS power transistors within compact area, a 2D distributed in-phase power combiner is utilized. Moreover, digitally-assisted self-tuning biasing is introduced for power back-off efficiency improvement, where DC power is reduced along with output power. One digitally-assisted 4-way power-combined PA prototype was implemented in 65nm CMOS process with measured output power of 17.2dBm, PAE of 11.3%, and up to 170~190% efficiency improvement during power back-off for the entire 7GHz band at 60GHz.