Yuanhua Chen

DC voltage balancing technique using multi-pulse optimal PWM for cascade H-bridge inverters based STATCOM

A novel multi-pulse optimal PWIM technique for STATCOM based on cascade H-bridge inverters is proposed. The harmonics are suppressed using optimization techniques. Furthermore the fundamental output voltages of all the inverter cells are controlled to be equal to make all the inverter cells equally share the exchanged power with power system, which is to maintain the dc voltages as balance as possible. At the same time the switching-pattern swapping technique is used, and the dc voltages can be fairly balanced. The validity of the proposed method is verified using the experimental results of a laboratory prototype of 30 kVAr STATCOM based on a 17-level cascaded H-bridges inverter.

DSP-based universal space vector modulator for multilevel voltage-source inverters

A novel simple, fast and generally applicable multilevel space vector modulation (SVM) algorithm is proposed in this paper. The reference voltage vector is decomposed into offset vector and two-level vector. Thus a complicated multilevel SVM issue is simplified into a simple two-level SVM issue. The switching states and their duty cycle are determined based on the zero-sequence reference voltage and a good combination of switching states selection and optimal control of inverters is reached. The proposed algorithm is very simple, fast and applicable for any number of levels. Based on the proposed SVM algorithm, a DSP-based universal space-vector modulator for multilevel inverters is developed. The validity of the proposed algorithm and the developed modulator is verified by the test results of various numbers of levels. It is also verified using a 6 kV/1800 kVA three-level inverter system.

FPGA-based universal multilevel space vector modulator

This paper presents a new circuit design of multilevel space vector modulation (SVM) strategy. This strategy is based on the decomposition of the reference voltage, and it is utilized at any number of levels. The proposed algorithm has been realized using field programmable gate array (FPGA) technology. A FPGA XILINX XC2S100 was used for the implementation of the SVM IC. The designed SVM IC was incorporated with a digital signal processor (DSP) to provide a solution for a three-phase five-level inverter. Experimental results are provided to verify the implemented SVM control IC

6 kV/1800 kVA medium voltage drive with three-level NPC inverter using IGCTs

This paper presents a 6 kV motor drive consisting of a 24-pulse rectifier and a three-level neutral-point-clamped (NPC) inverter using IGCTs. It is suitable for feeding standard industrial motors. Experimental results from the industrial installation show that the design and the implementation are successful.

Development of a scaled STATCOM prototype based on 21-level cascade H-bridge inverter

This paper is intended to present a laboratory scaled STATCOM prototype using 21-level cascade H-bridge inverter, which is developed to verify the control schemes that will be adopted in a plusmn50 MVar STATCOM project. A novel multi-pulse optimal PWM technique for STATCOM based on cascade H-bridge inverters is proposed. The harmonics are suppressed using optimization techniques. Furthermore the fundamental output voltages of all the inverter cells are controlled to be equal to make them equally share the exchanged power with power system, which is to maintain the DC voltages as balance as possible. Combined with the switching-pattern swapping technique, the DC voltages can be fairly balanced. The redundant operation is achieved through storing switching angles for various cases of N. A nonlinear control scheme based on the theory of exact linearization via feedback is proposed to improve the dynamic performance of the STATCOM. The validity of the proposed method is verified using the experimental results of the laboratory scaled prototype

Analysis of high di/dt current pulses in three-level NPC inverters using series connected IGCTs and RC snubbers

High di/dt current pulses are harmful to the safety of IGCTs, especially to the low current conducting or freewheeling conducting IGCTs. This paper comprehensively analyzes the current pulses that flow through the inner switch of a three-level NPC inverter with series connected IGCTs and RC-snubbers. Four cases of high di/dt current pulses are addressed. The moments at which the high di/dt current pulses occur are clearly demonstrated. The value of the corresponding di/dt is estimated as well. The analysis is verified through simulation results using PSCAD/EMTDC. Based on the comprehensive analysis, the methods to handle these high di/dt current pulses are given respectively. An external re-trigger system is designed for a 6 kV/1800 kA three-level NPC inverter-fed medium voltage drive using series connected IGCTs. A more safe and reliable operation is reached for the series connected IGCTs in the three-level NPC inverter.