Yuanqing Li

Supply Voltage Dependence of Heavy Ion Induced SEEs on 65 nm CMOS Bulk SRAMs

Soft Error Rates (SER) of hardened and unhardened SRAM cells need to be experimentally characterized to determine their appropriate applications in radiation environments. This characterization is especially important when low supply voltage is preferred. In this paper, we developed an SRAM test chip with four cell arrays including two types of unhardened cells (standard 6T and subthreshold 10T) and two types of hardened cells (Quatro and DICE). This test chip was fabricated in a 65 nm bulk technology and irradiated by heavy ions at different supply voltages. Experimental results show that the SERs of 6T and 10T cells present significant sensitivities to supply voltages when the particle linear energy transfers (LETs) are relatively low. For Quatro and DICE cells, one does not consistently show superior hardening performance over the other. It is also noted that Quatro cells show significant advantage in single event resilience over 10T cells although they consume similar areas. TCAD simulations were carried out to validate the experimental data. In addition, the error amount distributions follow a Poisson distribution very well for each type of cell array.

Analysis of advanced circuits for SET measurement

Single Event Transients (SETs) are a growing concern in advanced integrated circuits yet techniques to accurately characterize the cross-section and pulse width of SETs are less mature than those for measuring SEUs. We present four circuits for measuring SETs, an analysis of their capabilities and the subtleties in their implementation. Post-layout circuit simulation results are presented for a test-chip implemented in 28 nm FSDOI technology and integrating these detectors.

Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree

Abstract The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.

BPPT — Bulk potential protection technique for hardened sequentials

In this paper, we present a method for hardening memory and sequential cells against soft errors. The effect of the ionizing particle on the bulk potential is exploited to prevent the induced SET from propagating in the circuit. The proposed method requires a minimum number of extra transistors. The solution is applied to D Flip-Flop design, and alpha and heavy-ions test results are presented.

Single Event Transient and TID Study in 28 nm UTBB FDSOI Technology

Measuring single-event transient (SET) pulse widths is critical for developing proper mitigation schemes to single-event effects (SEE), especially for advanced technologies. This paper presents a test chip design implementing advanced techniques for measuring SETs implemented in a 28 nm Ultra-Thin Body and Box (UTBB) FDSOI technology. Experimental results of heavy ion and Co-60 irradiation experiments are presented. The heavy ion experiments confirm that this technology has very low SEE sensitivity. Laser test results show that pulse distortion (broadening) plays a key role when evaluating the effect of SETs. Total Ionizing Dose (TID) effects were also evaluated by measuring the Ring Oscillator (RO) frequencies and static current during heavy ion and Co-60 irradiation. Experimental results showed that the RO frequencies degraded up to 10% (heavy ion), and 40% (Co-60) after 1000 krad(Si) irradiation, but the logic in the chip functioned without error.

A novel asymmetrical SRAM cell tolerant to soft errors

In this paper, we propose a novel asymmetrical 11T SRAM cell design that has fault correction capability. In addition, the Layout design through Error-Aware transistor Positioning (LEAP) technique is adopted in designing the layout of this proposed 11T cell. The area of the proposed 11T cell without using LEAP technique (regular 11T) is 76% larger than that of traditional 6T cell and 16% larger than that of the Quatro cell. The area of 11T cell with LEAP technique (LEAP-11T) is 15% larger than that of regular 11T cell and 103% larger than that of 6T cell. Simulation results show that the error cross section of regular 11T is 17X lower and 2.8X lower than that of traditional 6T at LET = 10 and 30 MeV-cm2/mg respectively in normal strikes; and it is 2.2X lower than Quatro cell when LET = 30 MeV-cm2/mg in normal strikes. With LEAP technique implemented, the LEAP-11T cells error cross section is 6.5X lower than the Quatro cell when LET = 10 MeV-cm2/mg in angled strikes.