Yuchun Chang

Digital background calibration of MDAC stage gain error and DAC error in pipelined ADC

A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudo-random sequences into the MDAC. With this method, not only small capacitors might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined ADC could be replaced by low gain low power counterparts, which results in improving the figure-of-merit (FOM) significantly. A 12-bit 100MS/s pipelined ADC achieves 11.934 bits ENOB and 101.22dB SFDR, compared with 7.685 bits and 50.95dB without calibration.

A Dual-Mode High-Voltage High-Efficiency Peak-Current-Mode Asynchronous Buck Converter

This paper proposes a high-voltage high-efficiency peak-current-mode asynchronous DC–DC step-down converter operating with dual operation modes. The asynchronous buck converter achieves higher efficiency in light load condition compared to synchronous buck converters. Furthermore, the proposed buck converter switches operation mode automatically from pulse-width modulation (PWM) mode to pulse-skipping mode (PSM). By reducing power MOS on-state resistance and optimizing rise/fall time of switches, the proposed buck converter also obtains high efficiency under heavy load condition. The maximum efficiency of the proposed buck converter is 92.9%, implemented with 0.35μm BCDMOS 2P3M process, and the total size is 1.1× 1.2mm2. The input range and output range of the converter are 6–30 V, and (Vinput–3) V, respectively, with the maximum output current of 3 A. Moreover, its built-in current loop leads to good transient response characteristics. Therefore, it can be used widely in communication system and 12 V/24 V distributed power system.

10-bit 20MS/S differential SAR ADC for image sensor

Low-power and small-area implementations are essential in the CMOS image sensor market. At the same time, to achieve high-accuracy and high-speed is very important for ADC studying. This paper presents the design of a 10-bit 20MS/s differential Successive Approximation Register (SAR) ADC with a new switching procedure using for CMOS image sensor application. Compared with conventional 10-bit ADC, the number of capacitors is reduced by 50% and the average switching energy consumption is reduced by 81.26%. The ADC is fabricated in 0.18um CMOS technology and occupies an active area of 750×135um2. The ADC shows a SNDR of 61.33dB, a SFDR of 77.09dB, and an ENOB of 9.89bits with a 566.4KHz sinusoidal input at 20MS/s sampling frequency. The ADC consumes about 750uW at 1.8V supply.

A fully on-chip LDO regulator with a novel PSRR boosting circuit

A novel PSRR boosting circuit is presented to improve mid-frequency power supply rejection ratio (PSRR) of fully on-chip low dropout regulator (LDO). With this method, the zeros of PSRR are rearranged in a nested Miller compensation (NMC) based fully on-chip LDO. The mid-frequency PSRR is boosted when the dominant zero of PSRR is moved to higher frequency by the PSRR boosting circuit. Fabricated with GSMC 0.18μm CMOS process, the LDO features a -63dB PSRR at 100 kHz and about -40dB at 1MHz.

A 12-bit cyclic ADC for image sensor

This paper describes a low-power fully differential cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuits. The Cyclic ADC with redundant signed digital (RSD) algorithm has various obviously advantages, such as simpler circuit configuration and more tolerance to offset error of comparator. An operational amplifier with gain-boosting is used to increase the accuracy of the ADC. A prototype ADC is fabricated in 0.15um 1P6M CMOS technology. The results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 72.4dB and a spurious free dynamic range (SFDR) of 80.4dB. The power dissipation is 140uW with a 5V supply, and the chip size is 9um×570um.

A background calibration technology for capacitance mismatch in pipelined ADCs with 2.5-bit/stage MDAC

In traditional pipelined ADCs, errors originated by capacitance mismatch, finite amplifier gain, incomplete settling and offset. To overcome capacitance mismatch for >=2.5-bit/stage MDAC architecture, a new background digital calibration strategy is proposed in this paper. Based on this technique, a 14-bit, 40MS/s pipelined ADC is implemented. The simulation results show that ENOB is improved from 9.7 bits to 13.3 bits with σ=0.5% capacitance mismatch within 1s. The chip is fabricated in 0.18um CMOS process, occupied an active area of 4×4mm2, including on-chip decouple capacitors, with 110mW power consumption at 3.3 V.

A high Dynamic Range CMOS image sensor with dual charge transfer phase

A high dynamic range CMOS image sensor (CIS) with dual charge transfer phase is presented. The proposed method enhances the DR (Dynamic Range) of CIS by generating two branch of reset and charge transfer control signal TG according to the incident light intensity. Compared with conventional techniques, the method presented in this paper shows linear response in all light intensity range. The proposed CIS pixel architecture is implemented with 0.18 um 1P4M standard CIS technology. The DR of CIS with the proposed architecture reaches to 107.36 dB with 46.21 dB enhancement with only 5% additional power consumption.

A 2-V 40-MS/s 14-bit pipelined ADC for CMOS image sensor

The paper describes the implementation of a 40-MS/s 14-bit pipelined analog-to-digital converter (ADC) for CMOS image sensors in 0.18μm CMOS technology. The pipeline architecture consists of a series of 2.5bit stages, one stage 2-bit flash ADC and time align & digital error correction circuit. The ADC design is provided with a differential input voltage range of ±1V, 3.3 V power supply, and a total power dissipation of 100mW in typical case. The ADC achieves a SNDR of 82.4dB and ENOB of 12.6bits at 40MHz sample rate with a sine wave input of 17 MHz frequency. The entire ADC chip occupies 2.5mm×0.9mm area. The ADC in this design meets the requirement of CMOS image sensors well.

A 12-bit 500KSPS cyclic ADC for CMOS image sensor

At present, single-slope analog-to-digital convertor (ADC) is widely used in the readout circuits of CMOS image sensor (CIS) while its main drawback is the high demand for the system clock frequency. The more pixels and higher ADC resolution the image sensor system needs, the higher system clock frequency is required. To overcome this problem in high dynamic range CIS system, this paper presents a 12-bit 500-KS/s cyclic ADC, in which the system clock frequency is 5MHz. Therefore, comparing with the system frequency of 2N×fS for the single-slope ADC, where fS, N is the sampling frequency and resolution, respectively, the higher ADC resolution doesn’t need the higher system clock frequency. With 0.18μm CMOS process, the circuit layout is realized and occupies an area of 8μm×374μm. Post simulation results show that Signal-to-Noise-and-Distortion-Ratio (SNDR) and Efficient Number of Bit (ENOB) reaches 63.7dB and 10.3bit, respectively.

14-bit pipeline-SAR ADC for image sensor readout circuits

A two stage 14bit pipeline-SAR analog-to-digital converter includes a 5.5bit zero-crossing MDAC and a 9bit asynchronous SAR ADC for image sensor readout circuits built in 0.18um CMOS process is described with low power dissipation as well as small chip area. In this design, we employ comparators instead of high gain and high bandwidth amplifier, which consumes as low as 20mW of power to achieve the sampling rate of 40MSps and 14bit resolution.