Yugui Qu

A queue management MAC protocol for Delay-Tolerant Mobile Sensor Networks

For Delay-Tolerant Mobile Sensor Networks with highly dynamic and sparse topology, a queue management MAC protocol (Q-MAC) is proposed in this paper. Via the scheme of data transfers initiated by the targeted sinker and dynamic queue management strategy, Q-MAC provides better network performance. Furthermore experimental results show that Q-MAC reaches to 46% decreases in packet drop probability, 79% increase in system throughput, and 25% decrease in the mean packet delay.

An energy-efficient MAC protocol using dynamic queue management for delay-tolerant mobile sensor networks.

Conventional MAC protocols for wireless sensor network perform poorly when faced with a delay-tolerant mobile network environment. Characterized by a highly dynamic and sparse topology, poor network connectivity as well as data delay-tolerance, delay-tolerant mobile sensor networks exacerbate the severe power constraints and memory limitations of nodes. This paper proposes an energy-efficient MAC protocol using dynamic queue management (EQ-MAC) for power saving and data queue management. Via data transfers initiated by the target sink and the use of a dynamic queue management strategy based on priority, EQ-MAC effectively avoids untargeted transfers, increases the chance of successful data transmission, and makes useful data reach the target terminal in a timely manner. Experimental results show that EQ-MAC has high energy efficiency in comparison with a conventional MAC protocol. It also achieves a 46% decrease in packet drop probability, 79% increase in system throughput, and 25% decrease in mean packet delay.

A pipelined processor architecture for regular expression string matching

The expressive power of regular expressions has been often adopted in network intrusion detection systems, virus scanners, and spam filtering applications. However in the CPU based systems, pattern matching is one of the most computation intensive parts. In this paper, we present the design, implementation and evaluation of a regular expression string matching processing unit (SMPU). This special purpose processor is a parallel and pipelined architecture which can deal with the regular expression semantics. Two hardware stacks are implemented in SMPU to support fast branches when the non-matching occurs. Our implementation processes four characters per clock cycle (maximum performance of state of the art solutions) and occupies only O(n) memory (where n is the length of the regular expression) via synthesizing the verilog description and analyzing area/time constraints, SMPU can achieve 200-400 times speedup over traditional CPU implementations and up to 7.9Gbps in processing throughput. Besides it outperforms the counterparts greatly as the complexity of regular expressions increases.