Yuichi Gomi

A rolling-shutter distortion-free 3D stacked image sensor with −160dB parasitic light sensitivity in-pixel storage node

Conventional CMOS image sensors widely used in products currently on the market are mainly equipped with a rolling exposure function. This rolling exposure causes so-called “Jell-o effect” distortion when capturing a moving target. CMOS image sensors with a global-shutter function are one of the solutions to avoid this distortion. An in-pixel storage node is required to create a global-shutter CMOS image sensor. A floating diffusion and an additional capacitor can be used as an in-pixel storage node [1,2]. The light sensitivity of the in-pixel storage node is specified by the parasitic light sensitivity (PLS), which is the ratio of the light sensitivity of an in-pixel storage node and the light sensitivity of a photodiode. The PLS should be small enough so that the in-pixel storage is not light-sensitive. Artifacts are captured in an image from bright moving objects during read-out if the PLS is not small enough. The PLS of reported global-shutter CMOS image sensors is around -100dB. That would be small enough to use those image sensors in fields where the light source can be controlled. However, for DSC usage, users can easily encounter scenes with bright objects (e.g. sunlight or car headlights). Even if the in-pixel storage node is light-shielded, it is difficult to perfectly protect the in-pixel storage node from photo-generated carriers, as long as the in-pixel storage node and a photodiode are on the same silicon substrate. Meanwhile, 3D stacking technologies have been introduced for image sensors to give them more functionality and improved performance [3,4]. The reported minimum interconnection pitches for image sensors are over 20μm. These technologies do not fit the smaller pixel pitches of the image sensors in recent DSCs. In this paper, we report a rolling-shutter distortion-free 3D stacked image sensor with an in-pixel storage node of -160dB parasitic light sensitivity. The image sensor virtually achieves a global-shutter function using a 4-times frame-shutter operation. The image sensor has 2 semiconductor substrates, where 1 substrate has a backside-illuminated photodiode array and the other a storage-node array. The image sensor achieves a PLS level of -160dB. The image sensor has 8.6μm pitched interconnections, and an interconnection yield of over 99.9% is achieved.

A 3D stacked CMOS image sensor with 16Mpixel global-shutter mode and 2Mpixel 10000fps mode using 4 million interconnections

A 16Mpixel 3D stacked CMOS image sensor with pixel level interconnections using 4,008,960 micro bumps at a 7.6μm pitch, which set no layout restriction and causes no harm to sensor characteristics, was developed to achieve both a 16Mpixel global-shutter mode with a -180dB PLS and 2Mpixel 10000fps high speed image capturing mode.

3-D-Stacked 16-Mpixel Global Shutter CMOS Image Sensor Using Reliable In-Pixel Four Million Microbump Interconnections With 7.6-

We have developed a 3-D-stacked 16-Mpixel, 3.8-μm pitch, and global shutter (GS) CMOS image sensor with a 2-Mpixel 10 000-frames/s high-speed image-capturing mode, with four million reliable microbump interconnections. This sensor consists of a photodiode (PD) substrate and an in-pixel storage node substrate. The four PDs in the unit pixel circuit on the top substrate share one microbump interconnection in 7.6-μm pitch. Each signal of the PDs is transferred to the corresponding storage node on the bottom substrate via the interconnection to achieve a GS function. The ratio of the parasitic light sensitivity of an in-pixel storage node and the light sensitivity of a PD is -180 dB, which is the best record for a CMOS image sensor with 3.8-μm pixels. The image sensor was fabricated with a wafer-on-wafer bonding process technology. We confirmed that the bonding process did not harm the pixel or the MOS transistor characteristics and required no extra area, which means no restrictions on the layout design of microbumps or circuits. No reliability problems were observed in either a heat cycle test or a high temperature and high humidity test.

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We developed an efficient method for evaluating the 4 million micro-bump interconnection resistances of the 3D stacked 16-Mpixel CMOS image sensor by including vertical scanning and readout circuits and extra circuits in both of two substrates for a resistance testing mode, which enables us not only to find failed bumps but also to evaluate the resistances by scanning all micro bumps. We measured the resistances of the interconnections ranging from 50 to 500 kΩ with a resolution of 50kΩ.

Pitch

We demonstrated multiband imaging with a multi-storied photodiode CMOS image sensor (CIS), which comprises two individually functioning layered devices that achieve optimized images in different substrates bonded by 3D technology. The sensor is able to capture a wide variety of multiband images, which is not limited to conventional visible RGB (Red Green Blue) images taken with a Bayer filter or to invisible infrared (IR) images, at the same time without any color or image degradation even with an extra IR light source. Its wide range sensitivity enables us to select the specific narrow band light wave with specific optical filter in addition to visible RGB images. This wide selection of specific wavelengths of light is useful for specific applications like medical systems to identify pathological lesions and also enables additional functions on the same sensor to make such systems smarter, smaller, and cheaper than the conventional combination of IR imaging sensors with RGB image ones. A wide selection of multiband images is also possible with our device by modifying the top semiconductor layer thickness or changing the characteristics of a color filter on the top substrate to cover a wide range of application needs.

An efficient method to evaluate 4 million micro-bump interconnection resistances for 3D stacked 16-mpixel image sensor

We have developed a 3D stacked 16M-pixel, 3.8-μm pixel pitch, global-shutter CMOS image sensor with pixel level interconnections using four million micro bumps. The four photodiodes in the unit pixel circuit on the top substrate share one micro-bump interconnection at a 7.6-μm pitch. Each signal of the photodiodes is transferred to the corresponding storage node on the bottom substrate via the micro bump. This 3D architecture gives the image sensor not only a 16M-pixel global-shutter function but also a 2M-pixel 10K-fps high-speed image capturing mode with a burst of eight images. In this paper, we report on the improvement in the high-speed image capturing mode to operate at up to 100K fps by optimizing the timing for the higher-speed |image capturing with 2M-pixel resolution. In addition, we estimated the further potential of the 3D image sensor for high-speed image capturing to make the most of the 3D structure, which comprised one photodiode in the pixel unit circuit on the top substrate and electrically connected multiple storage nodes on the bottom substrate. This enables the image sensor to capture a burst of as many frames as the number of storage nodes in the pixel unit without sacrificing a photodiode and have better sensitivity with photodiodes fully occupying the chip surface with bigger photodiodes than when using conventional sensors. These results demonstrate that our 3D stacking technology pushes the envelope of capturing high-speed images with monolithic sensors.

Multi-storied photodiode CMOS image sensor for multiband imaging with 3D technology

We developed a multiband imaging CMOS image sensor (CIS) with a multi-storied photodiode structure, which comprises two photodiode (PD) arrays that capture two different images, visible red, green, and blue (RGB) and near infrared (NIR) images at the same time. The sensor enables us to capture a wide variety of multiband images which is not limited to conventional visible RGB images taken with a Bayer filter or to invisible NIR images. Its wiring layers between two PD arrays can have an optically optimized effect by modifying its material and thickness on the bottom PD array. The incident light angle on the bottom PD depends on the thickness and structure of the wiring and bonding layer, and the structure can act as an optical filter. Its wide-range sensitivity and optimized optical filtering structure enable us to create the images of specific bands of light waves in addition to visible RGB images without designated pixels for IR among same pixel arrays without additional optical components. Our sensor will push the envelope of capturing a wide variety of multiband images.

A 3D stacked global-shutter image sensor with pixel-level interconnection technology for high-speed image capturing

We developed and reported on a 3-D stacked CMOS image sensor (CIS) with a massive number of micro-bump interconnections placed at a narrow pitch between silicon substrates that pushes the envelope of CIS functions. The resistances of the interconnections were measured to be less than one hundredth of an ohm per bump with a test structure. There were, however, a small number of defective micro bumps with much higher impedance among the four million interconnections of the sensor. We developed a method for distinguishing defective interconnections from other defects and evaluated all interconnection resistances in a short amount of time with additional circuits in the CIS with reduced variable factors by using a modified current flow mode. This method makes it possible not only to identify defective interconnections but also to measure their impedances with less fluctuation.

Multiband Imaging CMOS Image Sensor with Multi-Storied Photodiode Structure †

Our 3D stacked CMOS image sensor (CIS) has an ideal global shutter function with 16 million pixels and 4 million micro-bump interconnections placed at a 7.6-εm pitch between two silicon substrates, achieving interconnections with very low resistance. We confirmed the reliability of our 3D stacked interconnection technology by conducting reliability tests, which included heat cycle tests and high temperature and high humidity tests. The interconnections in our image sensor are comprised of 4 million micro bumps per chip. No increase in the number of failed interconnections or in micro-bump interconnection resistance was observed. For the heat cycle tests, our CIS is designed to have two test modes to detect failed interconnections by scanning all 4 million micro-bump interconnections in a short period. In the high temperature and high humidity tests, we tested the reliability of the interconnections by using test element group (TEG) chips to monitor the resistance precisely. We evaluated the effects of wafer bonding and the micro bumps on a MOS transistor with the TEGs, comparing two types of structures, one with micro bumps and one without, located under an nMOS transistor, and no difference in Vth among them was observed. These results prove that our 3D technology is reliable enough to be applied to our products.

Characterization of 4 Million Micro-Bump Interconnections at 7.6-

We developed a novel 3D stacked CMOS image sensor that not only improved the leakage characteristics by changing the applied voltage to storage nodes and reduced random noise in global shutter operation by using increased capacitors but also simultaneously captured the interval image of the rolling shutter operation between global shutter operations.