Yuichi Kawakami

Advanced single-chip signal processor

A CMOS single chip signal processor, which has 32-bit floating point arithmetic units and large capacity on-chip memories, has been developed. The processor, having a floating point parallel multiplier, a floating point accumulator, two 512- word data RAMs, a 1024-word data ROM and a 2048- word program ROM, is implemented within a 15.4 × 8.4 mm chip area, containing 370,000 elements. As the processor is designed to perform highly accurate multiply-accumulate operations for digital filtering and to attain complex addressing capability for FFT computation, this processor can execute FIR computation at the 150 nsec per tap rate, as well as achieve 1024 point complex FFT computation in 12.3 msec.

LSI signal processor development for communications equipment

A single chip, versatile digital signal processor has been developed, which enables compact and low cost telecommunications equipment realization. The processor architecture has been optimized for real time voiceband signal processing by adopting efficient micro-program control and by integrating a 16 × 16 bit parallel multiplier on a single chip. The processor is fabricated with N-channel MOS technology, and operates at a clock speed up to more than 8 MHz. Any instruction, including multiplication, can be performed within a 250 nanosecond interval. The paper also describes applications to actual voiceband communications equipment to prove the processor effectiveness.

A microprocessor for speech recognition

A new single-chip microprocessor for speech recognition has been developed utilizing multi-processor architecture and pipelined structure. By DP-matching algorithm, the processor recognizes up to 340 isolated words or 40 connected words in realtime.

A Microprocessor for Speech Recognition

A new single-chip microprocessor for speech recognition, the SRP, has been developed, utilizing a multiprocessor architecture and a pipelined structure. It can recognize up to 340 isolated words or 40 connected words in real time. The SRP contains a vector distance calculator, a DP-equation calculator, and an I/O controller operating in a pipelined manner. Algorithm variations and operation parameters are user programmable, and the total size of the SRP program for a typical speech recognition system is about 700 words. The device has been fabricated with n-channel Si-gate E/D MOS technology with 2.5 μm design rules and employs 7296 three-transistor dynamic RAM cells for a total of more than 40 000 transistors.