Yuichi Saito

A strategy for avoiding pipeline interlock delays in a microprocessor

Pipelining of instruction execution significantly improves computer performance, but high dependencies between instructions limit the maximum concurrency that is achievable by pipelining. A hardware scheme to avoid pipeline interlock delays caused by dependencies in address generation is proposed. This scheme is implemented in the 32-b microprocessor M32/100. The M32/100 has a hardware interlock mechanism with scoreboard registers and a working stack pointer that is modified prior to the execution of each instruction. A simulator has been written and several benchmarks have been executed to investigate the performance achieved by these schemes.<<ETX>>

A 32-bit microprocessor based on the TRON architecture: Design of the GMicro/100

The special features of the GMicro/100 are covered, including the branching and pipelining methodologies as well as system modeling and verification. The GMicro/100 design strategies are briefly described.<<ETX>>

A 32-bit microprocessor with high performance bit-map manipulation instructions

The GMICRO/100, a 32-b microprocessor based on the TRON architecture specification, is described. The GMICRO/100 uses high-level instructions, such as those in bit-map manipulation. The bit-map instructions are implemented by pipelining micro-operations, and achieve optimum use of the memory bus in the execution. The bit-map instructions are 2 to 3 times faster than repeating move instructions by the software. Microprogram development tools for the GMICRO/100 design are described.<<ETX>>

A 32-bit superscalar microprocessor with 64-bit processing and high bandwidth DRAM interface

This paper describes a 32-bit CISC superscalar microprocessor designed for high-end embedded applications, such as X-window terminals and printers. To realize high performance of processing a series of memory data such as a frame buffer and a character-string, we have used block-data-transfer and 64-bit processing to improve execution efficiency of multiple-operation instructions of the processor. 16-byte block read/write operations through a 32-bit external data bus have accomplished high bandwidth for DRAM access, even in the case of non-cacheable regions such as a frame buffer. In executing multiple-operation instructions, 64-bit processing has been realized by operating the dual execution circuits for superscalar executions and a 64-bit internal data bus under the control of a very long micro-instruction word. By using these techniques, we have enhanced the frame buffer manipulation performance of this processor 1.5 to 2 times.<<ETX>>

A 32-bit superscalar microprocessor G/sub MICRO//400 for embedded systems

This paper describes a 32-bit superscalar microprocessor G/sub MICRO//400, based on the TRON architecture specifications. The G/sub MICRO//400 has a dual issued instruction pipeline, a pre-jump mechanism and a high-speed memory access interface. To realize high performance in processing of series data such as frame buffer or character-strings, the G/sub MICRO//400 has improved the execution efficiency of multiple-operation instructions by block-data-transfer and 64-bit processing. In order to improve the task switching latency, the on-chip caches are used as a local memory in which the context blocks are stored. These techniques are suitable for realtime embedded systems, such as X-window terminals and printers. Using 0.5 /spl mu/m triple-layer metal CMOS technology, the G/sub MICRO//400 integrates 1485K transistors on a 108 mm/sup 2/ die area. The G/sub MICRO//400 achieves a processing speed of 45 MIPS at 40 MHz.<<ETX>>