Yuji Okuto

Junction Temperatures under Breakdown Condition

A method of determining the junction temperature under breakdown condition is described. The junction temperature T1 is calculated from the applied voltage and the current in the following equation: V1=VB0{1+β(T1-T0)}+I1ρsc0{1+γ(T1-T0)}, where V1 and I1 are the applied voltage and current, VB0 and ρsc0 are the breakdown voltage and the space charge resistance at the ambient temperature T0, and β and γ are the temperature coefficients of VB and ρsc, respectively. Based on this method, the burn-out temperatures of mesa-type Si p+–n junction diodes are found to be between 200~300°C. The cause of burn-out at such a low temperature is also discussed.

Computer Aided Si-MOSFET Process Designing

A computer program is developed, which simulates Si-MOSFET fabrication process and its electrical characteristics. In this program,one dimensional impurity distribution and oxide thickness are traced and Poissons equations with Maxwell-Boltzmann distribution function are solved. Process designing for an n-channel Si-gate E/D MOSIC is carried out. The predictions are in good agreement with the experimental results. Various process sensitivities can be estimated using this program. This program will be useful for process, device and circuit designing of MOSICs.

The Temperature Coefficient of the Breakdown Voltage of Si Abrupt Punched-Through Type Diodes

Experimental results on the temperature coefficient β of the breakdown voltage of punched-through type Si p+–n–n++ diodes are described. The increment of the breakdown voltage ΔV is proportional to both the increment of the junction temperature ΔT and the width of the punched-through space charge region Wn. β (≡ΔV/[ΔTVB]) can be expressed by β=\frac{2CW_{0}}{E_{\text{max}}(2W_{0}-W_{n})}, where C=constant, Emax=the maximum electric field at the junction and W0=the width of the punched-through space charge region calculated from the impurity concentration of n-layer. Values of β agree with those obtained by the simple theoretical relation of the ionization coefficient α.

SOS CMOS 16 Bit Parallel Multiplier

A high performance 16 by 16 bit parallel multiplier is presented, which features SOS CMOS configuration. Maximum multiplying time and average power are 65 ns and 250 mW (VDD=5 V), respectively. The SOS CMOS multiplier shows the best powerdelay product, compared with other device-configuration multipliers reported. This performance can be accurately reproduced by circuit simulation without including parasitic capacitance. Through this experimental study, the SOS CMOS advantage for logic LSI application was confirmed.

Fundamental performance limit of integrated systems

The performance limits of integrated digital systems in terms of the functional throughput have been evaluated using the uncertainty principle and the thermal limit. Parallel processing capability and the limited power dissipation for each system were used as parameters. It is shown that, while the operation is limited by the uncertainty principle, the maximum obtainable functional throughput increases by increasing the degree of parallel processing through increasing the switching time of elemental switches to reduce their switching power. It is also shown that, while the operation is thermally limited, the expected maximum functional throughput is independent of switching speed so long as sufficient parallel processing is realized.

SOS/CMOS as a High-Performance LSI Device

To realize a high performance LSI, devices used should satisfy the following requirements; 1) High speed operation, 2)-Low power consumption, 3) Easy designability and 4) Higher integration capability. SOS/CMOS has been examined both experimentally and theoretically for these aspects. Ideal CMOS operation with τpd∼100 psec with P.τ∼0.1pJ/action is obtained. 1 GHz operation is confirmed on 1/16 frequency dividers. Using the same device, maximum multiplying time, τmul∼ 25 nsec at 5 V with 1.5 mW average power at 10 MHz is obtained on a 4×4 parallel multiplier. The above result agrees with the estimation of the circuit simulation without including stray capacitance associated with wiring. The same simulation predicts τmul∼60 nsec with 200 m w at most at 16 MHz operation for a 16×16 parallel multiplier. Basic theoretical estimation predicts, for large scale integration, SOS/CMOS can operate much faster than NMOS and occupies less area than bulk CMOS.