Yuji Tanikawa

A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit

A microprocessor designed as a processing element of a scientific parallel computer system is described. This chip consists of a simple integer processor core and dedicated floating-point hardware and executes 64-bit floating-point addition, subtraction, and multiplication at a rate of every 50 ns and division every 350 ns. The processor, which employs RISC architecture and Harvard-style bus organization, executes most of the 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology, containing 440K transistors in a 14.4*13.5-mm/sup 2/ die. The authors provide an overview of the processor, especially focusing on the functions for a parallel system, floating-point hardware, and the new divide algorithm. >