Yuk Ying Chung

Handwritten character recognition by Fourier descriptors and neural network

This paper describes a handwritten character recognition system by using a multi-layer perceptron with one hidden layer. Features extracted from the handwritten characters are Fourier descriptor (FD) and border transition technique (BTT). The FDs and border transition values are input to the neural network which is then trained by backpropagation. Test results indicate that FD combined with BTT can provide good recognition accuracy (96%) for handwritten numerals 0 to 9.

Video Compression With Custom Computers

Custom computers are a new computing paradigm where reconfigurable logic in the form of SRAM-based field programmable gate arrays are used as a co-processor resource in addition to a conventional CPU. This allows application developers to adapt not only the software but also the hardware of the computer on an application-by-application basis. Experimental evaluation of computational speed for 2-D discrete cosine transforms of 8/spl times/8 pixel blocks within a 512/spl times/512 pixel image show that a custom computer can provide speedups of 50-100 times compared to state-of-the art computer workstations, confirming the applicability of custom computing for video processing applications.

Handwritten character recognition by contour sequence moments and neural network

Contour sequence moments (CSM) have been used in the classification of four closed planar shapes. Gupta et al. described a neural network approach for the classification of four closed planar shapes using a contour sequence. In this paper, a backpropagation neural network is used in the recognition of handwritten numerals (from 0 to 9) using contour sequence moments. Experimental results indicate that the neural network approach gives better recognition accuracy when compared with the two conventional statistical classifiers, namely the nearest neighbour and minimum-mean-distance. This CSM technique was compared with geometrical moment (GM) invariants. We found that the recognition accuracy for handwritten character using GSM and neural network is over 95% while GM invariants and neural network can only give 82%.

High accuracy handwritten character recognition system using contour sequence moments

Contour sequence moments (CSM) have been used in the classification of four closed planar shapes (Gupta and Srinath, 1987). Also a neural network approach for the classification of four closed planar shapes using a contour sequence is described by Gupta et al in the literature. In this paper, a back-propagation neural network based classifier is used in the recognition of handwritten numerals (from 0 to 9) using contour sequence moments. The network utilized is a multilayer perceptron (MLP) with one hidden layer. Experimental results indicate that the neural network approach gives better recognition accuracy as compared with the conventional statistical classifier: the single nearest-neighbour. The performance of the CSM technique was also compared with geometrical moment (GM) invariants. We found that the recognition accuracy for handwritten characters using CSM and the neural network is over 95% while GM invariants and neural network can only give 82%.

Implementing neural network in custom computers

This paper describes the implementation of a partially connected neural network using FPGAs (field programmable gate arrays) based custom computers. Starting from the training data, a decision tree is generated using the classifier program C4.5. The tree is then used to initialise the architecture of the neural network to a nearly optimum configuration. This initialised partially connected network is then trained using training data. The trained neural network is then implemented by fine-grain Xilinx XC6200 series FPGAs. This implementation requires fewer connections and can provide a very high speed classification for many real-time image recognition applications.

Custom computing implementation of two-step block matching search algorithm

Many fast search block-matching motion estimation (BMME) algorithms has been developed in order to minimize the search positions and speed up the computation but they do not consider how they can be effectively implemented by hardware. We propose a new regular fast search block-matching motion estimation algorithm named two step search (2SS). The 2SS BMME will then be implemented on the SPACE2 custom computer board which consists of up to 8 Xilinx XC6216 fine-grain, sea-of-gate FPGA chips. The experimental and simulation results show that it can have better algorithmic performance and can be implemented by FPGA chips very cost-effectively for video compression applications. Also, the 30 frames per second real time 2SS BMME video compression can be obtained from the SPACE2 custom computer.

High-speed neural network based classifier for real-time application

This paper describes how to implement a partially connected neural network by a Giga-Ops Spectrum G800 FPGA (field programmable gate arrays)-based custom computer which consists of up to 32 Xilinx XC4010 logic chips. From the training data, a decision tree is generated by the classifier program C4.5. The tree is then used to initialise the neural network to a nearly optimum configuration. This initialised partially connected neural network is then trained by training data. The trained neural network is then implemented by our custom computer system. This implementation requires fewer connections and can provide a very-high-speed classifier for many real-time image recognition applications.

Video compression on FPGA-based custom computers

The field programmable gate array (FPGA) based custom computer is a new computing paradigm which can provide fast and flexible processing. This paper describes the implementation of 2D DCT algorithms for video compression using a FPGA-based custom computer. Our experimental result shows that by using an FPGA-based custom computer, the speed for processing 2D discrete cosine transforms in video compression can be improved 50 to 100 times when compared with workstation or super-computer implementations.

Implementation of DCT for video compression with reconfigurable technology

Describes the implementation of discrete cosine transform (DCT) algorithms for video compression using reconfigurable logic technology. We present two approaches for the implementation of the DCT. We discuss their time and area limits using Xilinx 4010 look-up table (LUT) based field programmable gate array (FPGA). The result shows a 50% area reduction or 2 times throughput improvement if we use distributed arithmetic instead of conventional arithmetic to implement DCT using LUT-based FPGA.

Efficient implementation of the DCT-based video compression on custom computers

Custom computers are a new computing paradigm where reconfigurable logic in the form of SRAM-based field programmable gate arrays (FPGAs) are used as a co-processor resource in addition to a conventional CPU. This allows application developers to adapt not only the software but also the hardware of the computer on an application-by-application basis. The design of arithmetic circuits for FPGA-based custom computers is investigated, and it is demonstrated that look-up table based arithmetic circuits can provide significant performance benefits compared to conventional arithmetic. Experimental evaluation of computational speed for 2-D discrete cosine transforms of 8/spl times/8 pixels blocks within a 512/spl times/512 pixel image show that a custom computer can provide speedups of 50-100 times compared to state-of-the art computer workstations.