Yukio Kadowaki

An LSI implementation of generalized transversal filters

An LSI implementation of a programmable finite impulse response filter based on a generalized transversal filter structure is described. The overall structure is in the form of tapped and cascaded linear phase FIR subfilters which are processed in parallel. The LSI contains 52 different filters, any one of which can be selected by six external pins. Each filter is equivalent to a conventional filter with about 40-50 filter lengths, and has a maximum sampling rate of 1.11 MHz, the 5.0*5.5 mm/sup 2/ chip was fabricated using 1.5- mu m double-level metal CMOS technology. >

An implementation of a hierarchical generalized transversal digital filter

The authors have implemented the two-level hierarchical generalized transversal FIR filter. This chip included nine subfilters and four tapping parts. Each subfilter had exactly the same filter characteristics and the coefficients of each tapping part were the same. This highly parallel structure allowed the reduction of the number of control bits, the number of filter sequences, the chip size, and the operation time. It only needed up to 32 words and 16 bits of machine-level control sequence. Up to 21-MHz clock speed and 3 MHz sampling speed was available. The 5.4*5.5 mm chip was fabricated using 1.2- mu m double-level metal CMOS technology with 44 pins flat or PLCC package.<<ETX>>

LSI implementation of a programmable FIR digital filter

The implementation of a programmable FIR (finite impulse response) digital filter based on a generalized transversal filter structure consisting of tapped, cascaded, identical FIR subfilters is presented. The LSI chip includes 56 different filters. One of the desired filters can be selected by six external ins on the LSI. The specifications of each filter are as follows: (1) the passband ripple is less than 0.5 dB; (2) the attenuation in the stopband is more than 50 dB; and (3) the normalized transition band is less than 0.1. A maximum sampling rate of 1.11 MHz is realized by virtue of the parallel processing of the subfilters. The 5.0*5.5 mm/sup 2/ chip was fabricated using 1.5- mu m double-level-metal CMOS technology.<<ETX>>