Yun-Heub Song

Statistical Characterization of Noise and Interference in NAND Flash Memory

Given the limited set of empirical input/output data from flash memory cells, we describe a technique to statistically analyze different sources that cause the mean-shifts and random fluctuations in the read values of the cells. In particular, for a given victim cell, we are able to quantify the amount of interference coming from any arbitrarily chosen set of potentially influencing cells. The effect of noise and interference on the victim cell after repeated program/erase cycles as well as baking is also investigated. The results presented here can be used to construct a channel model with data-dependent noise and interference characteristics, which in turn can be utilized in designing and evaluating advanced coding and signal processing methods for flash memory.

Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories

A new NAND string and its read operation scheme using self-boosting as a solution for improving read disturb characteristics of NAND flash memories are proposed. By using the proposed self-boosting read scheme, which includes an optimized bias voltage and adjusted threshold voltage (Vth) of dummy cells, the self-boosted channel voltage prevents soft-programming in unselected memory cells during read operation due to reduced electric field across tunnel oxide. Compared to the conventional scheme this leads to a significant improvement in read disturb characteristics. From simulation and measurement results, the worst electric field of the proposed NAND flash memory during read operation is decreased by around 50% and Vth shifts caused by read disturb is lowered by around 40%, compared to conventional NAND. The proposed NAND was fabricated in a 60 nm NAND technology and successfully demonstrated.

The threshold voltage fluctuation of one memory cell for the scaling-down NOR flash

The threshold voltage (Vth) fluctuation for the NOR flash memory scaling is investigated. The Vth fluctuations for one memory cell in 45nm node are dramatically increased to 350% compared to 90nm generation due to the reduction of channel area and the increase of channel doping level. Here, as the cell size is scaled, the impact due to random telegraph noise (RTN), Dopant Fluctuation and etc become more critical. In 45nm technology, the RTN results in the Vth fluctuations of 60% from the measurement results. Furthermore, we also propose one solution with the channel doping engineering to suppress the Vth fluctuations. It is confirmed that maximum RTS amplitude at the center can be significantly decreased to below 20% in 45nm technology by the modification of channel doping profile. From this result, the Vth fluctuations within one NOR flash cell are the most critical issue for the cell size scaling, and can be effectively suppressed by the optimal channel engineering.

Ultrashallow Junction Formation by Rapid Thermal Annealing of Arsenic-Adsorbed Layer

Ultrashallow junction formation in sub-0.1 µm metal oxide semiconductor field effect transistor (MOSFET) fabrication has been focused on as a key process technology. In this work, the arsenic (As) doping method, with rapid thermal annealing of the As-adsorbed layer with a capping oxide, was investigated for the first time as a technique for shallow junction formation. The As-adsorbed layer is successfully fabricated by AsH3 injection into the gas-source molecular beam epitaxy (GSMBE) apparatus. As-layer doping provides an extremely shallow junction (Xj: 20 nm) with a low sheet resistance (below 2 kΩ/sq.), thus proving to be a superior technique for shallow junction formation in the source/drain extension region of N-channel MOSFETs.

Inverse Resistance Change Cr2Ge2Te6-Based PCRAM Enabling Ultralow-Energy Amorphization

Phase-change random access memory (PCRAM) has attracted much attention for next-generation nonvolatile memory that can replace flash memory and can be used for storage-class memory. Generally, PCRAM relies on the change in the electrical resistance of a phase-change material between high-resistance amorphous (reset) and low-resistance crystalline (set) states. Herein, we present an inverse resistance change PCRAM with Cr2Ge2Te6 (CrGT) that shows a high-resistance crystalline reset state and a low-resistance amorphous set state. The inverse resistance change was found to be due to a drastic decrease in the carrier density upon crystallization, which causes a large increase in contact resistivity between CrGT and the electrode. The CrGT memory cell was demonstrated to show fast reversible resistance switching with a much lower operating energy for amorphization than a Ge2Sb2Te5 memory cell. This low operating energy in CrGT should be due to a small programmed amorphous volume, which can be realized by a high-resistance crystalline matrix and a dominant contact resistance. Simultaneously, CrGT can break the trade-off relationship between the crystallization temperature and operating speed.

Fabrication of Vacuum-Sealed Capacitive Micromachined Ultrasonic Transducer Arrays Using Glass Reflow Process

This paper presents a process for the fabrication of vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT) arrays using glass reflow and anodic bonding techniques. Silicon through-wafer interconnects have been investigated by the glass reflow process. Then, the patterned silicon-glass reflow wafer is anodically bonded to an SOI (silicon-on-insulator) wafer for the fabrication of CMUT devices. The CMUT 5 × 5 array has been successfully fabricated. The resonant frequency of the CMUT array with a one-cell radius of 100 µm and sensing gap of 3.2 µm (distance between top and bottom electrodes) is observed at 2.84 MHz. The Q factor is approximately 1300 at pressure of 0.01 Pa.

Bidirectional Two-Terminal Switching Device Using Schottky Barrier for Spin-Transfer-Torque Magnetic Random Access Memory

We present a bidirectional two-terminal switching device using a Schottky barrier for spin-transfer-torque magnetic random access memory (STT-MRAM), which is composed of a Schottky barrier contact with a metal/semiconductor/metal (M/S/M) structure. The proposed M/S/M switching device provides a bidirectional current flow sufficient to write STT-MRAM using a punch through with an extended depletion region at a junction under a reverse bias of M/S or S/M. In addition, a high on–off ratio of 105 is confirmed under the read condition, which is acceptable for the operation of STT-MRAM. From this work, it is expected that an M/S/M structure with bilateral Schottky junctions will be a promising switch device for STT MRAM beyond 20 nm.

Bidirectional Two-Terminal Switching Device for Non-Volatile Random Access Memory

A two-terminal N+/P/N+ Si junction device that can replace the conventional selective transistor was studied as a bilateral switching device for spin transfer torque magnetic random access memory (STT-MRAM), by three-dimensional device simulation. An N+/P/N+ junction structure with 30×30 nm2 area provides sufficient bidirectional current flow to write data by a drain-induced barrier lowering (DIBL) under a reverse bias at the N+/P (or P/N+) junction, and high current on/off ratio of 106, which is acceptable for STT-MRAM. In this work, critical parameters such as P-length, P doping, and N+ doping are investigated to elucidate the optimal parameter condition in view of write current and current on/off ratio.

Temperature dependence of reliability characteristics for magnetic tunnel junctions with a thin MgO dielectric film

Temperature dependence of the reliability characteristics of magnetic tunnel junctions (MTJs) with a thin (~1 nm thick) MgO dielectric film were investigated by numerical analyses based on the E-model, 1/E-model, and power-law voltage V-model, as well as by measuring time-dependent dielectric breakdown (TDDB) degradation. Although the tunneling process giving rise to TDDB is still under debate, the temperature dependence of TDDB was much weaker using the 1/E model than the E-model or power-law model. The TDDB data measured experimentally in CoFeB/MgO/CoFeB MTJ devices also showed rather weak temperature dependence, in good agreement with the numerical results obtained from the 1/E-model considering the self-heating effect in MTJ devices. Moreover, we confirmed by interval voltage stress tests that some degradation in the MgO dielectric layer occurred. Based on our findings, we suggest that to characterize the reliability of MTJs, combined temperature measurements of TDDB and 1/E-model analyses taking the self-heating effect into account should be performed.

Novel Self-Reference Sense Amplifier for Spin-Transfer-Torque Magneto-Resistive Random Access Memory

A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard 0.18 mm CMOS process. The proposed selfreference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.