Yusuf Leblebici

Dynamic thermal management in 3D multicore architectures

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and delay problems associated with the interconnects by reducing the length of the wires going across the chip. However, 3D integration introduces serious thermal challenges due to the high power density resulting from placing computational units on top of each other. In this work, we first investigate how the existing thermal management, power management and job scheduling policies affect the thermal behavior in 3D chips. We then propose a dynamic thermally-aware job scheduling technique for 3D systems to reduce the thermal problems at very low performance cost. Our approach can also be integrated with power management policies to reduce energy consumption while avoiding the thermal hot spots and large temperature variations.

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show Ion/Ioff > 106 and S ≈ 64mV/dec (70mV/dec) for p(n)-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor

This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a -3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 μVrms and the power consumption is 7.92 μW from a 1.8-V supply, which corresponds to NEF = 3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are - 43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256 μm × 256 μm in 0.18-μm complementary metal-oxide semiconductor technology.

A capacitive threshold-logic gate

A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-of-product and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described.

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Next-generation digital high-speed links require fast, yet energy-efficient ADCs at minimum area. Recent years saw impressive progress in SAR ADC designs towards higher sampling speed. Asynchronous clocking, redundant capacitive DACs (CDAC), multi-bit decisions per step and interleaved designs have been presented. We present an asynchronous redundant single-channel ADC achieving 1.2GS/s at 1V supply by using two comparators in alternation to relax comparator reset timing. The ADC achieves 39.3dB SNDR and 34fJ/conversion-step with a core chip area of 0.0015mm2.

Design considerations for CMOS digital circuits with improved hot-carrier reliability

The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F) and the transistor aspect ratio (/spl tau/) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability.

CMOS compressed imaging by Random Convolution

We present a CMOS imager with built-in capability to perform Compressed Sensing coding by Random Convolution. It is achieved by a shift register set in a pseudo-random configuration. It acts as a convolutive filter on the imager focal plane, the current issued from each CMOS pixel undergoing a pseudo-random redirection controlled by each component of the filter sequence. A pseudo-random triggering of the ADC reading is finally applied to complete the acquisition model. The feasibility of the imager and its robustness under noise and non-linearities have been confirmed by computer simulations, as well as the reconstruction tools supporting the Compressed Sensing theory.

Neuromorphic Computing Using Non-Volatile Memory

Abstract Dense crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing massively-parallel and highly energy-efficient neuromorphic computing systems. We first review recent advances in the application of NVM devices to three computing paradigms: spiking neural networks (SNNs), deep neural networks (DNNs), and ‘Memcomputing’. In SNNs, NVM synaptic connections are updated by a local learning rule such as spike-timing-dependent-plasticity, a computational approach directly inspired by biology. For DNNs, NVM arrays can represent matrices of synaptic weights, implementing the matrix–vector multiplication needed for algorithms such as backpropagation in an analog yet massively-parallel fashion. This approach could provide significant improvements in power and speed compared to GPU-based DNN training, for applications of commercial significance. We then survey recent research in which different types of NVM devices – including phase change memory, conductive-bridging RAM, filamentary and non-filamentary RRAM, and other NVMs – have been proposed, either as a synapse or as a neuron, for use within a neuromorphic computing application. The relevant virtues and limitations of these devices are assessed, in terms of properties such as conductance dynamic range, (non)linearity and (a)symmetry of conductance response, retention, endurance, required switching power, and device variability. Graphical Abstract

22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS

Forthcoming optical communication standards such as ITU OTU-4 and 100/400Gb/s Ethernet require ADCs with more than 50GS/s and at least 5 ENOB to enable complex equalization in the digital domain. SAR ADCs and interleaved ADCs made impressive progress in recent years. First CMOS ADCs with at least 6b and conversion rates exceeding 20GS/s were presented, proving that interleaved SAR ADCs are an optimal choice for high-speed ADCs with moderate resolution. We present an interleaved CMOS ADC architecture based on an asynchronous redundant SAR ADC core element. It was measured up to a sampling rate of 100GS/s and can be operated from a single supply voltage. At 90GS/s, the measured SNDR stays above 36.0dB SNDR up to 6.1GHz and 33.0dB up to 19.9GHz input frequency while consuming 667mW. The ADC is implemented in 32nm digital SOI CMOS and occupies 0.45mm2.