Yusuke Nonaka
Hitachi
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Publication
Featured researches published by Yusuke Nonaka.
international electron devices meeting | 2003
Takashi Hashimoto; Yusuke Nonaka; Tatsuya Tominari; H. Fujiwara; K. Tokunaga; M. Arai; S. Wada; T. Udo; M. Seto; M. Miura; Hiromi Shimamoto; Katsuyoshi Washio; H. Tomioka
200 GHz f/sub T/ SiGe HBTs and 80 nm gate CMOS were successfully integrated using the LP-CVD technique for selective SiGe epitaxial growth. Suppressing base resistance enabled us to achieve f/sub MAX/ of 227 GHz, corresponding to f/sub T/ of 201 GHz. Shrunk HBTs of A/sub E/=0.15/spl times/0.7 /spl mu/m/sup 2/ achieved ECL ring oscillator gate delay of 5.3 ps at Ics=1.2 mA. Self-heating effects on junction temperature and device performance were investigated with an emitter-width scaling effect. A low thermal budget HBT process sustains full compatibility with 0.13 /spl mu/m platforms for large scaled RF ICs.
international electron devices meeting | 2002
Takashi Hashimoto; Yusuke Nonaka; T. Saito; K. Sasahara; Tatsuya Tominari; K. Sakai; K. Tokunaga; T. Fujiwara; S. Wada; T. Udo; T. Jinbo; Katsuyoshi Washio; H. Hosoe
Without inducing any degradation of CMOS performance and reliability, a high performance self-aligned SiGe-HBT process was successfully integrated to a standard 0.13-/spl mu/m CMOS platform including dual gate oxides and five layers of Al metallization. Suppressing moisture elimination from a wafer surface is a key for reducing thermal budgets during the SiGe HBT formation process. We found that a heavily boron-doped intrinsic base that is highly activated by 1000/spl deg/C RTA improved HBT performance with low r/sub bb/ of 82 /spl Omega/ and high f/sub T//f/sub max/ of 122/178 GHz.
2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop | 2007
Yutaka Okuyama; Tomoyasu Furukawa; Tomohiro Saito; Yusuke Nonaka; Tetsuya Ishimaru; Kan Yasui; Digh Hisamoto; Yasuhiro Shimamoto; Shinichiro Kimura; Makoto Mizuno; Koichi Toba; Daisuke Okada; Takashi Hashimoto; Kousuke Okuyama
Lateral charge distribution in nitride of split-gate type semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memories has been determined by well-controlled experimental devices in which nanometer-size nitride piece was located at various positions for monitoring trapped charge. We found that electron distribution is created by two different hot-electron-injection mechanisms. Based on this new finding, the way to improve the matching of electron and hole distributions is investigated.
IEEE Journal of the Electron Devices Society | 2013
Takashi Hashimoto; Yusuke Nonaka; Tatsuya Tominari; Tsuyoshi Fujiwara; Tsutomu Udo; Hidenori Satoh; Kunihiko Watanabe; Tomoko Jimbo; Hiromi Shimamoto; Satoru Isomura
Hitachis SiGe BiCMOS technology, which integrates 0.18 μm CMOS and a SiGe heterojunction bipolar transistor (HBT), does not degrade MOS or bipolar performance. The BiCMOS process is divided into blocks, and the ordering of their processing is optimized so that they do not interfere with each other. Low-thermal-budget SiGe HBT formation is achieved using a minimal-moisture-desorption oxide layer, thereby avoiding disturbing the CMOS process. This technology, which can also be applied to the 0.13 μm generation, has been used for applications ranging from high-speed ones like automotive radar and 40 Gbps optical communication to consumer ones like wireless.
Archive | 2006
Yusuke Nonaka; Naoto Matsunami; Ikuya Yagisawa; Akira Nishimoto
Archive | 2011
Akihiko Araki; Yoshiki Kano; Sadahiro Sugimoto; Yusuke Nonaka
Archive | 2009
Junji Ogawa; Yoichi Mizuno; Yoshinori Ohira; Kenta Shiga; Yusuke Nonaka
Archive | 2008
Kenji Ishii; Yusuke Nonaka; Koji Nagata
Archive | 2006
Yusuke Nonaka; Akira Nishimoto; Azuma Kano
Archive | 2006
Yusuke Nonaka; Shoji Kodama; Tetsuya Shirogane