Yusuke Shirota

Powering-off DRAM with aggressive page-out to storage-class memory in low power virtual memory system

With the rapidly growing demands for large capacity main memory in server systems and embedded systems, current DRAM-only approach is hitting the limit due to DRAMs capacity scaling issue and significant background power. With the emergence of new non-volatile memories, or storage-class memories (SCMs), we can now explore low power, high capacity memory subsystem by redesigning virtual memory system to be SCM-aware. Most research on virtual memory system design has focused on minimizing page fault frequency due to slow data transfers using storage such as HDD/SSD as virtual memory swap device. However with an SCM-based swap device, its near-DRAM access latency has potential for reducing requisite DRAM size by aggressively evicting pages from DRAM to SCM without sacrificing performance, and thus reducing background power by powering off the freed DRAM space for low power. To select an optimal SCM from among the many candidate SCM technologies, the impact of SCM characteristics was evaluated using full-system simulation. Results show that utilizing SCM with low access latency and low write energy can lead to significant potential reduction of memory subsystem energy by up to 83%, while maintaining performance degradation within acceptable range.

Electronic Paper Display update scheduler for extremely low power non-volatile embedded systems

Aggressive use of low power modes in embedded systems using emerging non-volatile or low power compute state retainable devices can greatly reduce its power consumption of idle-state. However, in general, non-volatile devices require comparatively large power to switch between the stable states. Therefore, to realize extremely low power mobile platforms with powerful multimedia application processor running solely on photovoltaic-power, mitigating power consumption of its active-state is the next issue. Replacing power hungry conventional LCDs with non-volatile displays is inevitable in realizing such low power platforms, but naive replacement is insufficient. As such, low power control cognizant of non-volatile device properties is necessary[2]. We propose a display update request scheduling scheme designed for a promising non-volatile display: Electronic Paper Display(EPD) and give deep analysis of power consumption. Proposed scheme dynamically rearranges update requests ill-suited for EPDs to localized and collision-free low power consuming requests at the device driver level, reducing EPD-based tablets energy consumption by up to 49% without requiring application specific modifications.

Autotuning in an Array Processing Language using High-level Program Transformations

Abstract An autotuning framework based on an algorithm description language dedicated to array processing is introduced. The array processing language allows algorithm developers, may not be equipped with non-trivial knowledge of the increasingly complex architecture of todays processors, to easily perform extensive platform-specific tuning to fully extract performance. A given array processing program is translated into candidate parallel C codes, the best of which can then be selected by empirical evaluation. The high-level abstraction nature of our language allows a unique array processing program to be exposed to wide range of high-level program transformations, thus raising chances of obtaining high performance code. Furthermore, it also enables to extract algorithm-level information which can then be used in heuristic methods for efficient optimization parameter space exploration in the autotuning process. The results of preliminary evaluations show that autotuning using the parameterized C code variants generated with high-level program transformation is useful.