Yutaka Awata

An approach to LSI implementation of a 2B1Q coded echo canceler for ISDN subscriber loop transmission

An approach to large scale integration (LSI) implementation of the 2B1Q echo canceler for an integrated services digital network (ISDN) basic access interface is described. A hybrid architecture, using both analog and digital processing, is adopted for LSI implementation with a moderate circuit scale. Techniques using baud-rate sampling, such as square root f automatic gain control (AGC) equalization by power detection, timing extraction by peak estimation and a two-stage echo canceler with divided tables, are introduced to the system. Performance characteristics are also confirmed by computer simulation and a prototype system.<<ETX>>