Yutaka Kishi

Misfit dislocations in InP/InGaAsP/InP double‐heterostructure wafers grown by liquid phase epitaxy

The behavior of misfit dislocations in InP/InGaAsP/InP double‐heterostructure wafers grown by liquid phase epitaxy has been investigated by x‐ray and photoluminescence (PL) topography. Misfit dislocations were found to be generated from the edges of all the wafers studied here. X‐ray topographs for angle‐polished wafers show that misfit dislocations exist within the upper InP layer and are located in close vicinity to the heterointerface. PL topography has been used to determine the misfit dislocation‐free area within the wafers. This area decreases monotonically with the increase of the upper InP layer thickness, and is almost independent of the quaternary layer thickness. The lattice misfit is necessary to be in the range 0∼−0.08% at room temperature for making the area without misfit dislocations as wide as possible. Generation of misfit dislocations is considered to be strongly related to the ’’melt back’’ of the InGaAsP edge growth.

Heterojunction Effect on Spectral and Frequency Responses in InP/InGaAsP/InGaAs APD

Influence of the valence band discontinuity on the spectral and frequency responses in InP/InGaAsP/InGaAs APDs has been reported. Quantum efficiency showed gradual increases in the wavelength range from 1.0 to 1.3 µm, where the absorption coefficients decrease with increasing wavelength. Frequency response deteriorations, which cannot be explained by usual deterioration mechanisms, were found at around 300 MHz. These two characteristics are due to holes piled up at the heterointerface which was confirmed experimentally. Recombination and thermionic emission of piled up holes cause the deterioration of quantum efficiency and frequency response, respectively. High speed APDs are realized by increasing the electric field of the heterointerface in InP/InGaAsP/InGaAs APDs.

Misfit dislocations in (111)A InP/In0.53Ga0.47As/InP double heterostructure wafers grown by liquid phase epitaxy

The behavior of misfit dislocations in (111)A InP/In0.53Ga0.47As/InP double heterostructure (DH) wafers, grown by liquid phase epitaxy, has been investigated by x‐ray and photoluminescence (PL) topography and compared with those in (100) and (111) B quaternary DH wafers. Misfit dislocations are generated at wafer edges and are located in close proximity to the heterointerface in the upper InP layers. These dislocations were determined to be the same as in the case of (100) DH wafers. The misfit dislocation free area, as determined by PL topography with Ar+ ion laser excitation, decreases rapidly when the upper InP layer thickness approaches about 1 μm. Nearly misfit dislocation free DH wafers were obtained by a two step growth of the upper InP layer. In (111)A ternary DH wafers, with a lattice mismatch of 0% to −0.03% at room temperature, misfit dislocations are mostly β‐type 60° dislocations. These misfit dislocations are not observed by PL topography when ternary layers are excited by a Nd‐doped Yttrium...

Transmission Electron Microscopic Observation of Misfit Dislocation in InP/InGaAsP Double-Heterostructures

The nature and behaviour of misfit dislocations induced in InP/InGaAsP double-heterostructures grown by liquid-phase epitaxy were studied by transmission electron microscopy. Almost all of the misfit dislocations were of the 60° type, and pure edge dislocations and screw dislocations were very rarely generated. Other interactions between the misfit dislocations induced various types of reaction such as network formation, dissociation and pinning. The stacking fault energy in InP was determined from the distance between dissociated dislocations in the weak-beam image, as 55 erg/cm2.

Generation mechanism of misfit dislocations in In1−xGaxAs1−yPy/InP DH structure grown by LPE

Abstract Misfit dislocations in InP/InGaAsP/InP DH wafers have been investigated by X-ray transmission topography in relation to lattice mismatch measured by a double crystal X-ray diffractometer. The misfit dislocations are 60° dislocations and are generated in the top InP layer around the wafer periphery. The negative lattice mismatch between the top InP layer and the substrate is always observed in the region with misfit dislocations and is not observed in the region without misfit dislocations. With heat-treatment, most of the misfit dislocations are unaffected and some new ones are generated. The following generation mechanism is proposed: mobile 60° dislocations rapidly move toward the center region from dislocation sources at the wafer edges in the top InP layer during growth due to the lattice mismatch berween the top InP layer and the substrate and they move more easily in InP than in InGaAsP.

Liquid phase epitaxial growth of InP/InGaAsP/InP double‐heterostructure wafers free of misfit dislocations

A liquid phase epitaxial growth method for obtaining InP/InGaAsP/InP double‐heterostructure wafers free of misfit dislocations is presented. The feature of this method is that upper InP layers on InGaAsP are grown by two steps. The obtained structure becomes 2nd InP/1st InP/InGaAsP/InP. The misfit dislocation‐free area was determined by photoluminescence and x‐ray transmission topography. This area has been determined mainly at the stage when the growth of the first InP has been terminated and is scarcely dependent on the total thickness of the upper InP. Nearly misfit dislocation‐free wafers with about 4‐μm‐thick InP could be obtained by making the first InP thinner than ∼1 μm.

Low‐temperature impact ionization rates in (111) oriented InP

Impact ionization rates in (111) oriented InP have been derived in the temperature range 77–293 K from photomultiplication data measured on a planar‐type InP avalanche diode, and have been compared with those in (100) oriented InP. It has been found that there is no marked difference in electron ionization rates between the 〈111〉 and 〈100〉 orientations. This result confirms that no ballistic impact ionization occurs in InP at the measured electric field range of 4.1×105 V cm≤E≤5.6×105 V cm.

Reproducibility of low carrier concentration in LPE InP using batch melts

Abstract A useful and practical method for obtaining n-InP layers with low carrier concentrations by liquid phase epitaxy is presented. This method combines batch preparation of growth melts with compensation of residual donors by the p-type dopant Cd, and needs no long-term baking of the melts. The carrier concentrations could easily be controlled in the range of n = 1.0 x 10 15 -1.0 x 10 16 cm -3 b y varying the amounts of Cd in the batch-prepared melts. Good reproducibility of n = (4.5 ± 1.3) x 10 15 cm -3 has been obtained for 13 growth runs using the same kind of melts. Good uniformity of the carrier concentrations in n-InP layers was found within a wafer and along the growth direction.

Temperature dependence of critical supersaturation and interfacial tensions in In-P binary solutions

Abstract The critical supersaturation temperature in In-P binary solution was determined by the liquid phase epitaxial growth technique in the temperature range 570–750°C. Using the step-cooling method, the experimental values of the critical supersaturation temperature decreases from 31 to 10°C with increasing temperature. According to the classical homogeneous nucleation theory, the interfacial tensions between the solid and the liquid were estimated as a function of temperature. It was found that the interfacial tension tends to fall as the temperature increases.

Admittance Study of a Single Electron Trap in the LPE InP/InGaAsP Heterostructure Diode

Admittance spectroscopy is applied to the liquid phase epitaxial (LPE) InP/InGaAsP heterostructure diode with a Cd-diffused p+-n junction. A single electron trap is observed in the InP layer. The thermal activation energy is 0.55 eV, and the average capture cross section is 2.7×10-14 cm2 at temperatures 350 K–440 K. The cut-off frequency of the trap is about 30 Hz at room temperature. The trap concentration shows a sudden increase at the InP/InGaAsP heterointerface.