Yuya Minoura

Design and control of Ge-based metal-oxide-semiconductor interfaces for high-mobility field-effect transistors with ultrathin oxynitride gate dielectrics

High-quality Ge-based metal-oxide-semiconductor (MOS) stacks were achieved with ultrathin oxynitride (GeON) gate dielectrics. An in situ process based on plasma nitridation of the base germanium oxide (GeO2) surface and subsequent metal electrode deposition was proven to be effective for suppressing electrical deterioration induced by the reaction at the metal/insulator interface. The electrical properties of the bottom GeON/Ge interface were further improved by both low-temperature oxidation for base GeO2 formation and high-temperature in situ vacuum annealing after plasma nitridation of the base oxide. Based on the optimized in situ gate stack fabrication process, very high inversion carrier mobility (μhole: 445 cm2/Vs, μelectron: 1114 cm2/Vs) was demonstrated for p- and n-channel Ge MOSFETs with Al/GeON/Ge gate stacks at scaled equivalent oxide thickness down to 1.4 nm.

Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlOx) interlayers. A step-by-step in situ procedure by deposition of AlOx and hafnium oxide (HfOx) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO2/AlOx/GeOx/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlOx interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 1011 cm−2eV−1 with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

Interface engineering between metal electrode and GeO2 dielectric for future Ge-based metal-oxide-semiconductor technologies

Interfacial reactions between a metal-gate electrode and GeO2 dielectric in Ge-based metal-oxide-semiconductor (MOS) devices have been investigated by several analytical techniques, and we have demonstrated a method to suppress the interfacial reactions. Although no reaction occurs at the Au/GeO2 interface, a significant reaction was observed at the Al/GeO2 interface, which leads to increases in the leakage current and defect states in an MOS capacitor. While Al is oxidized at the Al/GeO2 interface, GeO2 is reduced to form Ge-Ge and Ge-Al bonding units during the early stage of the Al deposition. Moreover, the Ge-Al alloy segregates to the Al-electrode surface during the sequent Al deposition. These interfacial reactions are dramatically suppressed by insertion of ultrathin Al2O3 into the Al/GeO2 interface.

Understanding and engineering of NiGe/Ge junction formed by phosphorous ion implantation after germanidation

Modulation of the effective electron Schottky barrier height (eSBH) of NiGe/Ge contacts induced by phosphorous ion implantation after germanide formation was investigated by considering local inhomogeneity in the eSBH. Systematic studies of NiGe/Ge contact devices having various germanide thicknesses and ion implantation areas indicated the threshold dopant concentration at the NiGe/Ge interface required for eSBH modulation and negligible dopant diffusion even at NiGe/Ge interface during drive-in annealing, leading to variation in the eSBH between the bottom and sidewall portions of the NiGe regions. Consequently, this method makes it possible to design source/drain contacts with low-resistivity Ohmic and ideal rectifying characteristics for future Ge-based transistors.

Insights into thermal diffusion of germanium and oxygen atoms in HfO2/GeO2/Ge gate stacks and their suppressed reaction with atomically thin AlOx interlayers

The thermal diffusion of germanium and oxygen atoms in HfO2/GeO2/Ge gate stacks was comprehensively evaluated by x-ray photoelectron spectroscopy and secondary ion mass spectrometry combined with an isotopic labeling technique. It was found that 18O-tracers composing the GeO2 underlayers diffuse within the HfO2 overlayers based on Ficks law with the low activation energy of about 0.5 eV. Although out-diffusion of the germanium atoms through HfO2 also proceeded at the low temperatures of around 200 °C, the diffusing germanium atoms preferentially segregated on the HfO2 surfaces, and the reaction was further enhanced at high temperatures with the assistance of GeO desorption. A technique to insert atomically thin AlOx interlayers between the HfO2 and GeO2 layers was proven to effectively suppress both of these independent germanium and oxygen intermixing reactions in the gate stacks.

Phosphorous ion implantation into NiGe layer for Ohmic contact formation on n-type Ge

Low-resistivity Ohmic contacts on n-type germanium (Ge) together with ideal rectifying characteristics for p-type Ge were achieved using phosphorous-ion-implanted nickel germanide (NiGe). A pre-germanidation process prior to ion implantation was employed, and subsequent drive-in annealing at low temperature was used to precisely control the phosphorous profile and optimize the process conditions. Very low contact resistance on n-type Ge was demonstrated by using low-temperature drive-in annealing at 300 °C. Further process optimization (ion dose of 2 × 1015 cm−2; drive-in annealing at 400 °C for 30 min) resulted in an effective electron Schottky barrier height as low as 0.09 eV for n-type Ge and an on/off current ratio of five orders of magnitude for p-type Ge. The proposed low-temperature contact formation process offers a significant advantage in source/drain contact formation for Ge-based high mobility n-channel transistors.

Schottky source/drain germanium-based metal-oxide-semiconductor field-effect transistors with self-aligned NiGe/Ge junction and aggressively scaled high-k gate stack

Schottky source/drain (S/D) Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated by combining high permittivity (high-k) gate stacks with ultrathin AlOx interlayers and Fermi level depinning process by means of phosphorous ion implantation into NiGe/Ge contacts. Improved thermal stability of the metal/high-k/Ge stacks enabled self-aligned integration scheme for Schottky S/D complementary MOS applications. Significantly reduced parasitic resistance and aggressively scaled high-k gate stacks with sub-1-nm equivalent oxide thickness were demonstrated for both p- and n-channel Schottky Ge-FETs with the proposed combined technology.

Schottky barrier height reduction of NiGe/Ge junction by P ion implantation for metal source/drain Ge CMOS devices

We have demonstrated effective electron Schottky barrier height (eSBH) reduction of NiGe/Ge contacts using phosphorus ion implantation after germanidation. The eSBH was drastically reduced from 0.62 eV to 0.09 eV under optimum implantation and subsequent annealing conditions. Moreover, systematic studies of NiGe/Ge contacts with various P ion profiles indicated the variation in the eSBH at NiGe/Ge interface. This method allows us to design and control junction characteristics for future Ge-based devices.

Schottky barrier height modulation at NiGe/Ge interface by phosphorous ion implantation and its application to Ge-based CMOS devices

Our systematic studies of P-implanted NiGe/Ge junctions revealed the definite threshold in the P concentration for alleviating FLP and negligible P diffusion during drive-in annealing. These findings enable us to design the NiGe/Ge junction characteristics by modifying the device structure and implantation condition. We also demonstrated metal S/D p- and n-MOSFET operations with sub-1-nm EOT using the fabrication process flow of NiGe/Ge.

Sub-1-nm EOT Schottky source/drain Germanium CMOS technology with low-temperature self-aligned NiGe/Ge junctions

Schottky source/drain Ge-based n-and p-MOSFETs with sub-1-nm EOT and significantly reduced parasitic resistance were demonstrated for the first time. This technology involves two key processes: thermally stable high-quality metal/high-k/Ge gate stack and self-aligned formation of Fermi level pinned and unpinned NiGe/Ge junctions. The P+ implantation into embedded NiGe S/D and subsequent low-temperature annealing were effective in reducing effective electron Schottky barrier height (eSBH) at NiGe/Ge interfaces.