Yuzheng Ding

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height K-feasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUTs by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUTs by up to 50% compared to the three previous methods. >

Combinational logic synthesis for LUT based field programmable gate arrays

The increasing popularity of the field programmable gate-array (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGA-specific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a K-input one-output lookup-table (LUT) that can implement any Boolean function of up to K variables. This unique feature of the LUT has brought new challenges to logic synthesis and optimization, resulting in many new techniques reported in recent years. This article summarizes the research results on combinational logic synthesis for LUT based FPGAs under a coherent framework. These results were dispersed in various conference proceedings and journals and under various formulations and terminologies. We first present general problem formulations, various optimization objectives and measurements, then focus on a set of commonly used basic concepts and techniques, and finally summarize existing synthesis algorithms and systems. We classify and summarize the basic techniques into two categories, namely, logic optimization and technology mapping, and describe the existing algorithms and systems in terms of how they use the classified basic techniques. A comprehensive list of references is compiled in the attached bibliography.

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

Presents a polynomial time technology mapping algorithm, called Flow-Map, that optimally solves the lookup-table (LUT)-based field-programmable gate array (FPGA) technology mapping problem for depth minimization for general Boolean networks. This theoretical breakthrough makes a sharp contrast with the fact that the conventional technology mapping problem in library-based designs is NP-hard. A key step in Flow-Map is to compute a minimum height K-feasible cut in a network, solved by network flow computation. The algorithm also effectively minimizes the number of LUTs by maximizing the volume of each cut and by several postprocessing operations. The Flow-Map algorithm was tested on a a set of benchmarks and achieved reductions of both the network depth and the number of LUTs in mapping solutions as compared with previous algorithms.<<ETX>>

On area/depth trade-off in LUT-based FPGA technology mapping

In this paper, we study the area and depth trade-off in lookup-table (LUT) based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a sequence of depth relaxation operations and area-minimizing mapping procedures to produce a set of mapping solutions for a given design with smooth area and depth trade-off. As the core of the area minimization step, we have developed a polynomial time optimal algorithm for computing an area-minimum mapping solution without node duplication for a K-bounded general Boolean network, which makes a significant step towards complete understanding of the general area minimization problem in FPGA technology mapping. The experimental results on MCNC benchmark circuits show that our solution sets outperform the solutions produced by most existing mapping algorithms in terms of both area and depth minimization. >

On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping

In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous to subsequent re-mapping for area minimization. We then re-map the resulting network to obtain an area-minimized mapping solution. By gradually increasing the depth bound, for each design we are able to produce a set of mapping solutions with smooth area and depth trade-off. For the area minimization step, we have developed an optimal algorithm for computing an area-minimum mapping solution without node duplication. Experimental results show that our solution sets outperform the solutions produced by many existing mapping algorithms in terms of both area and depth minimization.

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs

We present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, named FlowSYN, uses the global combinatorial optimization techniques to guide the Boolean synthesis process during depth minimization. The combinatorial optimization is achieved by computing a series of minimum cuts of fixed heights in a network based on fast network flow computation, and the Boolean optimization is achieved by efficient OBDD-based implementation of functional decomposition. The experimental results show that FlowSYN improves FlowMap in terms of both the depth and the number of LUTs in the mapping solutions. Moreover, FlowSYN also outperforms the existing FPGA synthesis algorithms for depth minimization.

An improved graph-based FPGA technology mapping algorithm for delay optimization

A graph-based technology mapping algorithm, called DAG-Map, for delay optimization in lookup-table-based field programmable gate array (FPGA) designs is presented. The algorithm carries out technology mapping and delay optimization on the entire Boolean network, instead of decomposing it into fanout-free trees and mapping each tree separately as in most previous algorithms. As a preprocessing step, a general algorithm that transforms an arbitrary n-input network into a two-input network with only O(1) factor increase in the network depth is introduced. Also presented is a graph-matching-based technique used as a postprocessing step which optimizes the area without increasing the delay. The DAG-Map algorithm was tested on the MCNC logic synthesis benchmarks. Compared with previous algorithms, it reduces both the network depth and the number of lookup-tables.<<ETX>>

LUT-based FPGA technology mapping under arbitrary net-delay models

Abstract The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. Most existing algorithms for performance-driven technology mapping for Lookup-table (LUT)-based FPGA designs are based on the unit-delay model. In this paper we study the technology mapping problem under arbitrary net-delay models. We show that if the net delay can be determined or estimated before mapping, the problem can be optimally solved in polynomial time based on efficient network flow computation. We have implemented the algorithm and tested it on a number of MCNC benchmark examples.

On nominal delay minimization in LUT-based FPGA technology mapping

Abstract In this paper, we study the LUT-based FPGA technology mapping problem for delay minimization under the nominal delay model, which assumes that the interconnect delay of a net is proportional to the fanout size of the net. First, we show several complexity results on LUT mapping under the nominal delay model. We prove that the delay-optimal K- LUT mapping problem under the nominal delay model is NP-hard when K ≥ 3 , and remains NP-hard for duplication-free mapping and tree-based mapping when K ≥ 5 . Then, we show that for K = 2 the delay-optimal duplication-free mapping problem or tree-based mapping problem under the nominal delay model can be solved in polynomial time. Finally, we develop a heuristic LUT mapping algorithm for nominal delay minimization on general K- bounded Boolean networks. Experimental results have shown that our heuristic algorithm can produce mapping solutions of smaller delay compared with the solutions of the depth-optimal mapping algorithm under the unit delay model.

Placement and placement driven technology mapping for FPGA synthesis

Because of the more restrictive placement and routing constraints in Xilinx FPGA designs, conventional physical design tools for general placement and routing architectures usually do not work well for FPGA designs. Moreover, to generate high quality circuits which are easy to place and route, it is important to consider the specific physical design constraints during the technology mapping process. The authors first present a performance driven placement algorithm specifically developed for the Xilinx FPGAs. They then present a new placement driven technology mapping algorithm which uses placement information to guide the mapping process.<<ETX>>