Yves Leduc

Neural Network architecture for breast cancer detection and classification

Early detection of cancer or any disease is among the main keys to its cure. One of the state of the art methods in cancer detection is machine learning, namely ANNs (Artificial Neural Networks). ANNs have proved to be efficient due to their ability to learn and generalize from data. This paper proposes a low-complexity architecture of an ANN that classifies breast cancer as either Benign or Malignant through pattern recognition. It focuses on finding the optimal activation function that minimizes the classification error with less number of blocks. This results in reduction of the complexity of the implementation with CMOS technology.

UTBB-FDSOI complementary logic for high quality analog signal processing

An analog clock generator built with complementary logic cells in UTBB-FDSOI delivers the robust symmetrical clocks required to control high-performance differential switched-capacitor circuits. Using back-gate feedback and sizing respecting static and dynamic symmetry, the proposed solution is very tolerant to process inherent variations to the deep nanometer CMOS processes.

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

MOS bulk transistor is reaching its limits: sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage (VT) and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide (BOx). Called ultra thin body and buried oxide (UTBB) transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator (VCO) based on a ring oscillator (RO) designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about −94 dBc/Hz@1 MHz.

VCO design in SOI technologies

In this paper, we present the design of 2 PLL for low power Bluetooth applications, one in 130 nm PDSOI and the other in 28 nm FDSOI technologies. The PDSOI one is based on a classical LC tank VCO and uses the possibility of body contact to modulate the current core of the VCO in order to decrease the phase noise. Good performances in terms of phase noise are achieved with this technique, but we do not gain any size nor power consumption compared to a more classical bulk solution. This LC tank VCO is mandatory for such telecommunication applications. We propose to use a ring oscillator VCO to build a PLL in FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient backgate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise.

Novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology

In this paper, we propose a new complementary topology which could reduce the variability of the cells and offer new topologies with better performances. Using the unique advantage of FDSOI technology “back-gate control”, the complementary structure cross coupled inverters offering a fully symmetrical operation of complementary signals. It offers new solutions and new circuit structures of building blocks for PLL in 28nm UTBB-FDSOI technology.

New QVCO design using UTBB FDSOI technology

Researchers have predicted the end of the Moore law. One of the reasons is that MOS bulk transistor is reaching its limits: Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Threshold Voltage (Vth) and Vdd scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Up to now, the industrial solutions focus on silicon CMOS technology. To overcome the problem induced by aggressive technological 28nm node and beyond, the solutions are undoped channel devices. Two silicon technologies have emerged: FinFET and FDSOI. We have introduced the UTBB FDSOI technology in our lectures and practical activities under Cadence Labs. In this paper, we present a new inverter topology decreasing the process variability influence on performances of a ring oscillator. Using FDSOI technology, we propose a new complementary structure based on a pair of Back-gate cross-coupled inverters offering a fully symmetrical operation of complementary signals. Finally, we have studied the jitter of such ring oscillator and proposed some explanations.

Study and reduction of variability in 28 nm FDSOI technology

This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of a complementary inverter. This technique will reduce the variability of the inverter and the jitter (i.e. the phase noise) of the ring oscillator. Complementary cells allow us to implement back-gate auto-biasing feedback without adding transistors and to realize a quadrature ring oscillator with an even number of inverters.

Revamping a lab course for the education of students in electronic engineering

This is an ambitious academic tutored project, oriented to address the gap between standard university labs and real methods of designing ICs in the industry. Offering to our students a global view of the system, we allow them to better approach the PPAs (Power, Performance, Area) targets of each individual part. The learning is based on modeling, simulation, prototyping and characterization, as a fundamental way to understand behavior and key parameters. Several levels of difficulty are proposed to students in an incremental way: to design a Ring Oscillator from inverters and a Phase Frequency Detector (PFD) from CMOS existing gates; to switch to existing TI CMOS MicroPower PLL CD4046B; to use a full IC for sensor applications on smart buildings.